Device FA - DCG Systems

Role of FA in the Ramp of
Advanced Technologies
David Su
© 2013 TSMC, Ltd
1
Outline
 Introduction
 Packaging-Related FA
 Device FA
 Materials Analysis
 Summary
© 2013 TSMC, Ltd
2
Outline
 Introduction
 Packaging-Related FA
 Device FA
 Materials Analysis
 Summary
© 2013 TSMC, Ltd
3
Key Process Technology Features
0.13 um 90 nm
65 nm
45 nm
Metallization
LK
e SiGe
Gate stack
Transistor
structure
© 2013 TSMC, Ltd
16 nm
ELK
Strain Eng.
Patterning
20 nm
Cu
IMD
Lithography
28 nm
SiON/Poly
248 nm
HiK/MG
193 nm immersion
193 nm dry
Single patterning
Planar
Double patterning
FinFET
4
Transistor Performance Trend
 Strain and HiK/MG are key technologies in transistor
scaling
 New transistor structure and new material for next
generation transistor
Kuhn-Intel
IWJT2010
© 2013 TSMC, Ltd
5
Moore’s Law Viewed from the Failure and
Materials Analysis Engineer’s Perspective
 Increased Complexity (including 3-D Structures)
 New Materials
 Smaller Geometries
© 2013 TSMC, Ltd
6
What is the role of FA in the ramp of advanced
technology in the IC industry?
 Identify failure modes and the root causes of
failures with high success rate, high
throughput and high speed.
© 2013 TSMC, Ltd
7
Outline
 Introduction
 Packaging-Related FA
 Device FA
 Materials Analysis
 Summary
© 2013 TSMC, Ltd
8
Development Trends & FA Challenges for
Advanced Packaging
 Trends:

Cu bump to replace SnPb

Wafer-Level-Package

WLP/WLCSP & Fan-out WLP

Embedded technology

3D structure:

3DIC/2.5DIC and 3D package (PoP)
 The FA Challenges:
© 2013 TSMC, Ltd

Complex and multi-layer structure complicate detection of
light emission from defects.

Difficult sample preparation of complex, thin, and multi-layer
package materials.
9
Top FA Challenges Identified by the
Sematech Packaging and Interconnect
Failure Analysis Council (PIFAC)
 Package-Level Fault Isolation

Lock-In Thermography (LIT)
 Non-Destructive Fault Isolation

CSAM

TDR

3D X-ray
 Sample Preparation
© 2013 TSMC, Ltd

How to handle warped packages

FIB
10
Outline
 Introduction
 Packaging-Related FA
 Device FA
 Materials Analysis
 Summary
© 2013 TSMC, Ltd
11
Top Challenges Identified by the Integrated
Circuit Failure Analysis Council(ICFAC) of
Sematech
 Failure Isolation Precision (3D Volume)
 Barriers for Fault Isolation in New Technologies: e.g.
HiK/MG, FinFETs
 Non-Visible Defects
© 2013 TSMC, Ltd

Hot Carrier Injection (HCl), Negative Bias Temperature
Instability (NBTI)

Dopant-related failures

Charge trapping

Device matching
12
A Few Trends in Fault Isolation
 Design for Test and Scan Diagnosis
 Global Fault Isolation  Dynamic Fault Isolation
 Need for better electrical characterization of failures
 Nanoprobing
 EDA tool vendors’ “Yield Tools”
© 2013 TSMC, Ltd
13
Laser Voltage Imaging and Probing
 Varying Charge Density in the Space-Charge region modulates the
laser beam in amplitude and phase.

Change in space-charge region’s absorption coefficient (Amplitude
modulation)

Change in space-charge region’s index of refraction (Phase Modulation)
 LVI (Laser Voltage Image)
 LVP(Laser Voltage Probing)
© 2013 TSMC, Ltd
14
Applications of Laser Voltage
Imaging and Probing
LVI /LVP
& Tester
LVI
No LVI signal
© 2013 TSMC, Ltd
LVP
C189
DEL-1
BUF
DEL-2
C188
Dynamic Laser
Stimulation
Delay 60 ns
Fail site
Nano-Probing
 Equipment
 DCG n-Probe l and n-Probe ll (Zeiss supra55 SEM system)
with EBAC module and TCP
 Applications
 MOS transistor characterization (with temperature if need)


Transistor Id-Vg , Id-Vd, gate component, …etc
SRAM SNM measurement (Butterfly curve)
 BEOL failure isolation with EBAC
Probing System with 8 tips
From “http://dcgsystems.com”
© 2014 TSMC, Ltd
Outline
 Introduction
 Packaging-Related FA
 Device FA
 Materials Analysis
 Summary
© 2014 TSMC, Ltd
A Few Trends in Materials Characterization
 Heavy use of TEM for “metrology” applications
 Need for 3-D characterization and “metrology”
 Need for high spatial resolution and high
elemental/chemical sensitivity techniques
 High spatial resolution strain measurement
© 2014 TSMC, Ltd
18
A Few Trends in TEM Use in the IC Industry
 High Spatial Resolution: Aberration Correction, CsCorrected TEM or STEM.
 High Speed Energy Dispersive X-ray Analysis: Osiris
 Thinner samples <20nm or even <10nm
 Faster turnaround: Automation and Near-Line or InFab TEM
© 2013 TSMC, Ltd
19
Spherical Aberration Corrected TEM/STEM
0.136nm
Cs-corrector
Clear Si Dumbbell
STEM w/i Cs corrector
(STEM Probe Size=0.08nm)
Si Lattice
Thermal
shield
Magnetic
shield
Cannot resolve
Si Dumbbell
1
STEM w/o Cs corrector
(STEM Probe Size=0.2nm)
© 2013 TSMC, Ltd
Sample : Si<110>
20
Outline
 Introduction
 Packaging-Related FA
 Device FA
 Materials Analysis
 Summary
© 2013 TSMC, Ltd
21
FA in the Integrated Circuit Industry
 FA in Integrated Device Manufacturers (IDM):

Everything done “in-house”: Design debug, process
development, ramp, packaging, customer returns …
 The Foundry Perspective: an evolving model (still…)



© 2013 TSMC, Ltd
“Disintegration”:

Foundries limited to “Global” fault isolation

DFT and Scan Diagnosis…
Collaborative FA:

LVI: a major step forward

More dynamic fault isolation
What next?

Download Report