European LVDS devices - Indico

Use of IHP's 0.25 µm BiCMOS
Process in the Development
of European LVDS Devices*
AMICSA 2014 – CERN – GENEVA – SWITZERLAND
*EUROPEAN LVDS DRIVER DEVELOPMENT (ESA CONTRACT Nº. 4000105866)
Page  1
Outline
 ARQUIMEA / RAD HARD microelectronic products and services
 News!
 Introduction
 LVDS Octal Repeater
 Circuit Implementation
 Radiation Hardening
 Simulation Results
 Experimental Results
 Conclusions and Future Developments
 AOB
Page  2
AMICSA 2014
ARQUIMEA / RAD HARD MICROELECTRONIC
PRODUCTS AND SERVICES
MIXED-SIGNAL ASICs & IPs
• Deep submicron digital, analogue and mixed-signal design and
radiation hardening. SMART POWER.
• IP design, back-end and integration.
• ASICs Project Management (full supply chain).
TECHNOLOGY CHARACTERISATION
• Process or custom devices characterization (electrical and radiation test)
FPGAS
• Space FPGAs design and implementation as per ECSS-Q-ST-60-02
STANDARD COMPONENTS
• Development of rad hard standard components for space (LVDS,
ANALOGUE MULTIPLEXORS, ADC’s, DAC’s, …)
Page  3
AMICSA 2014
NEWS!
ARQUIMEA & IHP become partners in Space
microelectronics
Rad Hard Technologies
available for MPW & Small
Volume Production (under ESA
& DLR evaluation)
SGB25RH
SG13RH
Page  4
A cost-effective technology
with a set of RF npn-HBTs up
to a breakdown voltage of 7 V
A high-performance 0.13 µm
BiCMOS with npn-HBTs up to
=
250/300
GHz,
fT/fmax
with 3.3 V I/O CMOS and 1.2 V
logic CMOS
Rad-hard processes, libraries and IPs
for digital, RF, analogue & mixedsignal design
STEP
OUTPUT
CONTACT
1. Design Kit Access
Service
PDK (basic/enhanced)
IHP/
ARQUIMEA
2. Support to Design
VHDL/NETLIST +
SCHEMATIC
ARQUIMEA
3. Support to Analogue
Layout
VHDL/NETLIST +
SCHEMATIC + LAYOUT
ARQUIMEA
4. Support to A/D
Integration
GDSII FILES
ARQUIMEA
5. Automatic Test Pattern
Generation
TEST PATTERNS
ARQUIMEA
6. Netlist
NETLIST
ARQUIMEA
7. Place & Route
GDSII FILES
ARQUIMEA
8. Analogue Layout
ANALOGUE LAYOUT
ARQUIMEA
9. Analogue + Digital
Integration
GDSII FILES
ARQUIMEA
10. DRC + LVS Checks
GDSII FILES VERIFIED
ARQUIMEA
11. Manufacturing
CHIPS
IHP
12. Assembly & Test
TESTED PARTS
ARQUIMEA
13. Delivery
PARTS &
DOCUMENTATION
(including CoC)
ARQUIMEA
ARQUIMEA Projects
MIXED-SIGNAL ASICs & IPs
•
ELSA: Mixed signal housekeeping and conditioning device for Hispasat AG1
REDSAT active antenna to be launched in 2015.
•
DETECTA: High Speed Acquisition chain and ADC (>1 Gs, 10bit) based on
IHP 0.13um (2010).
•
•
•
Cosmic Vision HF & MF: Configurable mixed-signal ASIC for Cosmic Vision
Instrumentation Payload, for the following applications: CCD signal, processor,
Radiation detector, Radiation spectrometer, ADC, DAC, Filter, Low noise
amplifier, Power amplifier. Two devices at high frequency and medium
frequency are under development (2010).
European LVDS devices: Development of European Rad Hard LVDS
device family (2012).
RadHARQ: Development of rad hard digital library and radiation detectors
based on IT380 technology (2013).
•
SWIPE: Development of a radiation detector (TID, SEU) for moon lander
application (2013).
•
2014
CARTU: Development of a medium AMICSA
frequency
13-bit ADC (2013).
Page  5
Introduction
 Video, photo, high speed links, telemetries, … space systems
use very high data rates.
 Data links have to be:
– Fast
– Reliable
– Low Power
– Low EMI
– Low Cost
LVDS (Low Voltage Differential Signal) is used for
intra-spacecraft high speed communications.
Page  6
AMICSA 2014
LVDS
(Low Voltage Differential Signaling)
 Low Voltage Differential Signaling comprises the following advantages:
– High Data Rate
– Low Power
– Low EMI emissions
– High Noise Rejection
– Low Cost
 Its main characteristics are:
Source: National Semiconductor
– Differential
– Low voltage: ±350mV
– Common Mode Voltage: 1.2V
– Rise/Fall times: 260ps minimum.
– High Data Rate (655 Mbps max. ANSI/TIA/EIA-644 standard).
Page  7
AMICSA 2014
LVDS Topologies
Page  8
AMICSA 2014
LVDS Octal Repeater
COMMON BLOCKS
 Full ANSI EIA/TIA 644A compliance.
LVDS Octal
Repeater Block
Diagram
 Eight Data channels.
 One clock channel.
VDD
7,12,26,
37,42
END
1.24V
Bandgap
Reference
2.5V 2.5V
LDO
Regulator
3.3V
13,18,2
3,31,26
VSS
2
IN1+
43
+
IN1-
44
-
IN2+
45
+
IN2-
46
-
IN3+
3
+
IN3-
4
-
IN4+
5
+
IN4-
6
-
IN5+
8
+
IN5-
9
-
IN6+
10
+
IN6-
11
-
IN7+
14
+
IN7-
15
-
IN8+
16
+
IN8-
17
-
R1
30
OUT1+
29
OUT1-
28
OUT2+
27
OUT2-
D1
 Data channels enable pin.
 Clock channel enable pin.
R2
D2
 Tri-state driver capability.
 >500 Mbps data rate (250 MHz).
R3
22
OUT3+
21
OUT3-
D3
 Single 3.3 V Supply.
 Extended temperature range (-55ºC, +125ºC).
R4
20
OUT4+
19
OUT4-
41
OUT5+
40
OUT5-
D4
 Integrated voltage reference.
 Extended input common mode for LVDS inputs (-4V, +5V).
R5
D5
 Extended maximum absolute rating for LVDS inputs (-5V, +6V).
 TTL compatible digital inputs.
 Small channel delay, <2.7 ns typical, <3.5 ns over full temperature range.
 Low peak-to-peak jitter <236 ps (±3σ).
 Low channel to channel skew <150 ps typical, <250 ps over full temperature range.
 8 kV HBM ESD enhanced protection.
 Fail-Safe functionality included.
 Cold Spare functionality.
 Radiation Hardness higher than 300 kRad (Si) TID with ELDRS and SEL immune
up to 60 MeV cm2/mg LET.
 CQFP48 package.
Page  9
AMICSA 2014
R6
R7
R8
ENCK
47
CLKIN+
48
+
CLKIN-
1
-
R9
39
OUT6+
38
OUT6-
D6
35
OUT7+
34
OUT7-
33
OUT8+
32
OUT8-
D7
D8
25
CLKO+
24
CLKO-
D9
Circuit Implementation
 Receiver
– Frequency compensated Attenuation network
– Rail-to-rail high speed Comparator
– Fail-Safe Detector
– Fail-Safe 500ns RC timer
– Allows extended input common mode range from -4V to +5V
– Cold Spare inputs
Receiver
Amplifier
VREF
Input
PAD RIN+
OUTp
+
Rx
Comp
-
Logic
Control
Attenuator
Network
Input
RINPAD
OUTn
Extended
ICM
+
Fail-Safe
RC timer
Fail-Safe Condition
Detector
-
Fail-Safe
Page  10
AMICSA 2014
ROUT
(to driver
on-chip)
Circuit Implementation
 Driver
– Phase Splitter
– Driver Core
– Common Mode feedback amplifier
– Designed to achieve minimum at least 500Mbps data rate
– Cold Spare outputs
Common-mode
Feedback
CMF
+
Phase Splitter
DIN+
B1
DIN
(from receiver
on-chip)
B2
Vp
B3
DIN-
VREF
VCM
Vn
+
Driver
Core
-
OUT+ Output
PAD
OUTEND
Page  11
AMICSA 2014
Output
PAD
Circuit Implementation
 Bandgap
– 1.25V internal bandgap reference
– First order compensation
 Voltage Reference
– LDO regulator
– 3.3V input voltage
– 2.5V output voltage (core voltage)
 8 kV HBM ESD pads
–
Custom made ESD protections and
pads for 8kV ESD and 250V MM.
Bandgap output voltage across corner variations
Page  12
AMICSA 2014
Radiation Hardening
 Expected radiation performance of IHP SGB25RH (from previous
radiation data):
 Expected SEL immune > 60 MeV cm2/mg
 Immunity up to 300 kRad for high and low dose rates
 Several techniques were used to improve radiation hardness (in
addition to Rad Hard DRC design kit rules) including its application to
custom digital cells.
-
High W/L or ELT layout for NMOS devices.
-
Systematic guard ring isolations or triple-well isolation.
-
Differential design.
 SET sensitivity has been evaluated using specific software tools
(developed by Grupo de Ingeniería Electrónica, from Universidad de
Sevilla).
Page  13
AMICSA 2014
Radiation Hardening – SET simulation
SET Sensitivity
evaluation zone
SET injection
zone
Example of SET injection in the driver core circuitry
Page  14
AMICSA 2014
Radiation Hardening – SET simulation
Example of SET injection in the driver common mode feedback.
Driver CMRR avoids bit flip at the LVDS output.
Page  15
AMICSA 2014
Simulation Results
 Extensive extracted view simulations have been performed over:
 Full temperature range,
 Process corners,
 Supply variations.
 Results:
─ Full ANSI EIA/TIA 644A compliance.
─ Minimum Data Rate: 500 Mbps (can go up to 728Mpbs), with extended common mode
(-4V to +5V).
─ Small Channel delay: 2.7ns
─ Low channel to channel skew: 150 ps
─ Cold Spare, tri-state and fail-safe functionality verified.
Page  16
AMICSA 2014
Chip implementation
 IHP SGB25RH (MPW)
 Package: CQFP48
 Die size: 2x2 mm2.
(by MICROSS)
Page  17
AMICSA 2014
Test activities
 ESD testing has been performed by IHP achieving more
than 7.3kV for all pads (limited
by the test equipment capability).
 Full electrical characterization
in July 2014
 Radiation tests expected in
September 2014 (for TID and
heavy
ions)
by
ALTER
Technology.
LVDS Octal Repeater Test Board
Page  18
AMICSA 2014
Conclusions
 A radiation hard, Octal LVDS repeater has been designed and
manufactured.
─ Full ANSI EIA/TIA 644A compliance.
─ Minimum Data Rate of 500 Mbps (can go up to 728Mpbs), with extended common
mode (-4V to +5V).
─ Small Channel delay of 2.7ns
─ Low channel to channel skew of 150 ps
─ Cold Spare, tri-state and fail-safe functionality verified.
 Full electrical characterization and radiation testing ongoing.
 A full evaluation/qualification of the device it is expected to be performed
in the next project phase.
Page  19
AMICSA 2014
Future Developments
 A complete family of LVDS devices: driver, receiver, transceiver and
crosspoint switch, with equivalent performances to the octal repeater, are
under development by Arquimea as a continuation of this work.
COMMON BLOCKS
1.24V
Bandgap
Reference
2.5V
2.5V
LDO
Regulator
COMMON BLOCKS
3.3V
GND
16
RIN1-
1
+
RIN1+
2
RIN2+
3
-
+
RIN2-
4
13
DRIVER-1
DOUT2DOUT2+
ROUT1
RECEIVER-2
14
Bandgap
Reference
2.5V 2.5V
LDO
Regulator
3.3V
16,14,15,
19,21,34,
36
1A
38
+
1B
37
-
4X4
MUX
+
24
1Y
-
23
1Z
22
1DE
2A
33
+
+
8
2Y
2B
32
-
-
9
2Z
10
2DE
ROUT2
GND
VDD
3A
29
+
+
12
3Y
11
DIN2
3B
28
-
-
13
3Z
11
3DE
4A
3
+
+
18
4Y
4B
4
-
-
17
4Z
16
4DE
6
DRIVER-2
7
DOUT1-
8
GND
12
5
DOUT1+
10
DIN1
9
EN
S10-S40
1,2,26,
27,30,31,
39,40
Transceiver Block Diagram
Page  20
1.24V
EN
RECEIVER-1
15
5,7,20,
25,35
8
Crosspoint Switch Block Diagram
AMICSA 2014
for your attention…
[email protected]
Page  21
AMICSA 2014
arquimea_026
Microelectronics; Actuators; Space
Electronics
Microelectronics: Digital Design, Back-End
& Test Services
ARQUIMEA INGENIERÍA, S.L.U.
Margarita Salas 16 Bajo A, 28919
Leganés (Madrid) – ES
Phone: +34 91 689 8094
Email: [email protected]
Website: www.arquimea.com
Page  22
ARQUIMEA DEUTSCHLAND GmbH
Im Technologiepark 1,
15236 Frankfurt (Oder) – DE
Phone: +49 (0) 335 557 1717
Email: [email protected]
Website: www.arquimea.de
AMICSA 2014

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