Electronic Design Universidad de Alcalá Graduate in Communication Electronics Engineering Spartan-6 configuration Departamento de Electrónica What is configuration? – Process for loading configuration data into the FPGA Spartan-6 Family Configuration Data Source FPGA Control Logic (Optional) Diseño Electrónico 2 When does configuration happen? On power up On demand Why do FPGAs need to be configured? Spartan-6 Family FPGA configuration memory is volatile Configuration data is stored in a PROM or other external data source What do you need to know about FPGA configuration? What happens during configuration How to set up various configuration modes and daisy chains 3 Diseño Electrónico Spartan-6 Family FPGA Configuration Methods Xilinx PROMs: Slave/Master Serial Xilinx Cables: JTAG Slave Serial Slave SelectMAP Slave/Master SelectMAP FPGA Microprocessor: JTAG Commodity Flash: Slave SelectMAP Slave Serial Slave SelectMAP SPI* Diseño Electrónico BPI* 4 Configuration Pins Specific pins on the FPGA are used during configuration Spartan-6 Family Some pins act differently depending on the configuration mode Example: CCLK is an output in some modes and an input in others Some pins are only used in specific configuration modes 5 Diseño Electrónico Spartan-6 Family Configuration Pins Mode pins (3) Input pin(s) that select which configuration mode is being used PROGRAM_B Input that initiates configuration Active Low CCLK (configuration clock) Input or output (depending on configuration mode) Frequency up to 100 MHz (dependent on the FPGA, see configuration user guide) INIT_B Open-drain bi-directional pin Error and power stabilization flag Active Low DONE Open-drain bi-directional pin Indicates completion of configuration process DIN Serial input for configuration data DOUT Output to the next device in a daisy chain Used in daisy chains only …other pins are used for specific configuration modes Note that some configuration pins are dual purpose They become user I/O after configuration is complete − This is often prohibited by the user Diseño Electrónico 6 Configuration Modes Serial (one data line) JTAG − Primarily for debugging and prototyping, recommended for all applications, external control logic provided by download cable and JTAG chain Master Serial − Control logic is a part of the FPGA, uses serial Flash (such as Platform Flash Spartan-6 Family PROM) Slave Serial − External control logic is necessary, built by user SPI (Serial Peripheral Interface) − Control logic in FPGA, uses an industry-standard SPI Flash PROM, usually used in embedded applications Parallel (8-bit or 16-bit data lines) Master SelectMAP − Control logic is a part of the FPGA, uses parallel Flash (such as Platform Flash) Slave SelectMAP − External control logic necessary, built by user BPI (Byte-Wide Peripheral Interface) − Control logic is a part of the FPGA, uses an industry-standard NOR Flash, usually used in embedded applications 7 Diseño Electrónico JTAG Configuration Mode TCK is driven by your Xilinx programming cable The bitstream is stored on your computer and is downloaded via the ISE™ software iMPACT utility and a Xilinx programming cable Primarily used for debugging Control signals are in parallel Spartan-6 Family Unique programs are shifted into the appropriate device TCK ISE (iMPACT) + Cable TDO TDI FPGA TDO FPGA FPGA TMS TDO Diseño Electrónico 8 Master Serial Configuration Mode FPGA provides all control logic All mode pins are tied Low Slave serial mode requires Spartan-6 Family external control logic Xilinx Platform Flash PROM CCLK Data FPGA Master Serial mode FPGA drives configuration clock (CCLK) as an output Data is loaded 1 bit per CCLK Used when data is stored in a serial PROM (usually a Xilinx Platform Flash PROM) Slowest configuration mode, but the easiest to debug 9 Diseño Electrónico Slave Serial Configuration Mode External control logic required to generate CCLK Microprocessor or microcontroller Serial Data Data FPGA Spartan-6 Family Xilinx serial download cable CCLK Another FPGA could be used to build the control logic Daisy chains are often used in this mode Data is loaded 1 bit per CCLK Control Logic All mode pins are tied High Diseño Electrónico 10 Master SelectMAP Mode FPGA provides all control logic Sometimes called Master Parallel mode Spartan-6 Family FPGA drives address bus Data is loaded 1 byte per address Data internally serialized FPGA generates 8 CCLKs per byte CCLK Byte-Wide Data Source Data FPGA Usually targets Xilinx Platform Flash XL or another vendors Platform Flash PROM The Xilinx Platform Flash XL also works in BPI mode and is a popular memory resource for Virtex-5 and Virtex-6 This enable faster configuration times 11 Diseño Electrónico Slave SelectMAP Mode External control logic required (microprocessor or microcontroller, for example) Ready/Busy handshaking Data presented 1 byte at a time Spartan-6 Family Virtex-5 and Virtex-6 support x8, x16, and x32 Spartan-6 supports x8 and x16 Asynchronous Peripheral Control logic provides a Write strobe Triggers FPGA to generate 8 CCLK pulses Can target Xilinx Synchronous Peripheral CCLK provided by control logic (8 pulses per data byte) Platform Flash XL This would not require external control logic Byte-Wide Data Data Control Signals FPGA Ready/Busy Control Logic Diseño Electrónico 12 Serial Peripheral Interface (SPI) Mode FPGA configures itself from an attached industry-standard SPI serial Flash PROM FPGA issues a command to Flash and it responds with the data CCLK SPI Flash PROM Can be used in multi-boot applications where multiple bitstreams can be loaded by the FPGA Data Spartan-6 Family Data is loaded 1 bit per CCLK (slow) FPGA Command There are no standards for the commands Commands are vendor specific Vendor Select (VS) pins tell the FPGA which commands to issue Spartan™-6 supports x2 and x4 modes See Data Sheet or Configuration User Guide for list of supported vendors Excellent choice for embedded applications 13 Diseño Electrónico Byte-Wide Peripheral Interface (BPI) Mode FPGA issues an address to a BPI Flash, which responds with the data Uses standard parallel NOR Flash interface Spartan-6 Family No clock is needed because the FPGA contains the control logic BPI NOR Flash Data FPGA Addr[26:0] Usually used in embedded applications Flash is easily used as addressable memory with address and data buses Supported for Virtex™-5, Virtex-6, Spartan™-3E, and Spartan-6 FPGAs Xilinx Platform Flash XL is a 128 Mb parallel NOR and works in BPI and SelectMAP modes Spartan-6 BPI mode is shared with SelectMAP mode Diseño Electrónico 14
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