Discovery, Volume 19, Number 59, May 15, 2014 Design of Digital Phase Locked Loop using VHDL Sushma Mankar1, Khushbu Khapekar2, Usha Joshi3,Madhavi Vidhate4,Neha Digrase Department of Electronics and Telecommunication Engineering, Nagpur University, Nagpur 2 Smt. Rajshree Mulak College of Engineering for women 3 Great Nag Road, Nandanwan, Nagpur-440009.Nagpur University Email: [email protected], [email protected] I. INTRODUCTION PLLs are most common in applications like wireless transceivers, cellular phones, global positioning systems, etc. The PLL lock time is an important characteristic as it is the time a PLL takes to adapt to changes in the input frequency. Conventional PLLs employ phase tracking which takes a long time to lock, so they are misfits for contemporary highspeed high-throughput applications. The phase locked loop (PLL) is a very important and common part of high performance microprocessors. Traditionally, a PLL is made to function as an analog building block, but integrating an analog PLL on a digital chip is difficult. Analog PLLs are also more susceptible to noise and process variations. Digital PLLs allow a faster lock time to be achieved and are attractive for clock generation on high performance microprocessors. The digital phase locked loop was designed such that it is composed of four main components. The components are analogous to the analog PLL, but the implementation consists of digital components. The Phase Frequency Detector (PFD) detects the phase and frequency mismatch of the reference clock and VCO clock. The PLL is locked when the PFD detects that the phase and frequency of the two clock inputs match. The output of the PFD drives the charge pump. The PFD produces up and down enable signals that are interfaced to the charge pump. The charge pump converter takes these inputs and increases or decreases the control word which is fed to the low pass filter. This low Sushma Mankar et al. Design of Digital Phase Locked Loop using VHDL, Discovery, 2014, 19(59), 89-91, http://www.discovery.org.in/d.htm pass filter is essential for controlling the VCO and sent back to the PFD for phase and frequency comparison. The main components and their implementation will be discussed in the following sections. The implementation of the entire PLL contain VHDL based components. II. THEORY OF OPERATION A. Digital Phase/Frequency Detector The block diagram of the PFD is given . The inputsfor the PFD are the input clock and VCO output. The output UP/DOWN signals depend upon the lead/lag relationship between the two input signals. Ultimately, when the DPLL is locked both the UP and DOWN signals remain low. Fig. 2 describes a part of PFD implementation. B. Charge Pump (CP) and Lowpass Filter (LPF) The outputs of the PFD (UP and DOWN pulses) combined into single output for driving the LPF using a CP. The block diagram for the CP and LPF is given. The CP sources current into the LPF during the UP pulse to increase the output frequency and sinks current during the DOWN pulse to decrease the output frequency. The LPF consists of R2, C2, and C I. The voltage across C2 increases/decreases due to the PFDUP/DOWN pulses. C. Voltage-Controlled Oscillator (VCO) The VCO produces a digital pulse train whose frequency is proportional to the voltage across capacitor CI of the LPF. The VCO operating frequency is assumed to be 100MHZ II. DESIGN OF PLL SYSTEM COMPONENTS www.discovery.org.in © 2014 Discovery Publication. All Rights Reserved 89 Abstract—Digital phase locked loop(DPLL) is a closed loop frequency system that locks the phase of an output signal to an input reference signal. The term “lock” refers to a constant or zero phase difference between two signals. The Digital Phase Locked loop(DPLL) consist of the Phase Frequency Detector (PFD), the charge pump (CP), the low pass filter (LPF), and the voltage controlled oscillator (VCO). This design flow process included design and simulation of the components/system and it also included the VCO layout. The application we chose in designing the DPLL was a clock generator and frequency synthesizer. A clock generator generates a digital clock signal and a frequency synthesizer generates a frequency that can have a different frequency from the original reference signal. We are using VHDL language for simulation of DPLL on Xilinx software Index Terms –PLL ,DPLL, PFD,VCO,VHDL Page 1 Discovery, Volume 19, Number 59, May 15, 2014 The individual blocks of Fig. 1 are explained in thissection. Behavioral modeling for each block is also given 1. Phase Frequency Detector Out of the two inputs one is the input signal and the other is the output signal from the VCO. It compares the two pulse trains and produces a DC voltage which is proportional to the phase difference between the two frequencies. This voltage is known as the error voltage. Without the input signal, Ve and the VCO operates at a set frequency Fr which is also called free-running frequency of the VCO There are several characteristic of PFD which can be described as below: 1.A rising edge from the data and data1 must be present when doing a phase comparison. 2. The width of the data1 and the data is irrelevant. 3.The output of the "Up" and "Down" of the PFD are both low when the circuit is locked. Itwill cause the output of the filter a constant value 2. Internal Structure of PFD Internal structure of pfd contains of two D-Flip Flop and one AND Gate. The inputs of D-Flip Flop are input_c, D_in and reset. The output of D-Flip Flop is Q_Out 2.SIMULATION RESULT OF PHASE FREQUENCY DETECTOR Simulation result of Phase frequency detector is as shown above Phase frequency detector compared two frequencies a and b .If a>b then ouput of D flip flop 1 is activated .If a<b then ouput of D flip flop 2 is activated and If a=b then ouput of phase frequency is in locked state When ref rising edge(a) leads div rising edge(b) When ref rising edge(a) lags div rising edge(b) Sushma Mankar et al. Design of Digital Phase Locked Loop using VHDL, Discovery, 2014, 19(59), 89-91, http://www.discovery.org.in/d.htm When ref rising edge(a) leads div rising edge(b) www.discovery.org.in © 2014 Discovery Publication. All Rights Reserved Page Simulation result of D flip flop is as shown below Output of D flip flop depends upon input din and clock input .when clock is zero then output of D flip flop is reset i.e zero and When clock is 1 ,output of D flip flop will be din, it means that output is equal to input. 90 1.SIMULATION RESULT OF D FLIP FLOP Discovery, Volume 19, Number 59, May 15, 2014 When ref rising edge(a) is equal to div rising edge(b) Future scope of work: 1. A detailed Spice or BSIM model of MOS could be used to write a structural description of the PLL. Such an approach would help the bottom up verification of the design, and would make it more accurate. 2. A detailed noise analysis could be carried out and an accurate phase noise model could be developed. This would help predict correctly the relationship between the input power spectrum density and the closed loop transfer function. 3. The PLL can be made programmable and can be designed to have a wider lock range by making 3.SIMULATION RESULT OF VOLTAGE CONTROLLED OSCILLATOR some modifications to the design. This would necessitate the following design extension Simulation result of voltage controlled oscillator is as shown below. Voltage controlled oscillator converts voltage into frequency requirements: a) A programmable filter that can be selected based on the range of input frequency. b) A frequency meter at the input that tells an approximate value of the input frequency. c) A VCO designed to have a large bandwidth. REFERENCES [2] M. F. Wagdy and B. C. Cabrales, "A novel flash fastlocking digital phase-locked loop: design and simulations", Journal of the Institution of Engineering and Technology (lET), Circuits, Devices, and Systems, London, pp. 280-290, Vol. 3, Issue 5, October 2009. Page We would like to thank the Ms.Neha Digrase mam, for his constant support with debugging simulation errors and logical errors. Thank you to Professor Bagal sir for making this learning experience possible. 91 ACKNOWLEDGMENT [1]“An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors” Jim Dunning,, Gerald Garcia, Jim Lundberg, and Ed Nuckolls, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 4, APRIL 1995 Sushma Mankar et al. Design of Digital Phase Locked Loop using VHDL, Discovery, 2014, 19(59), 89-91, http://www.discovery.org.in/d.htm www.discovery.org.in © 2014 Discovery Publication. All Rights Reserved