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PRAGATI SACHAN et al.
DATE OF PUBLICATION: SEP 23, 2014
ISSN: 2348-4098
VOLUME 2 ISSUE 7 SEP-OCT 2014
BARRELSHIFTER
1PRAGATISACHAN,2ANCHALKATIYAR,3ANITADIDAL,4PALLAVIGAUTAM
M.TechScholar,VLSI,JayotiVidyapeethWomen’sUniversityJaipur,Rajasthan,INDIA,E‐mail:
,
[email protected] [email protected],[email protected],[email protected]
ABSTRACT
Barrelshiftersareoftenutilizedbyembeddeddigitalsignalprocessorsandgeneral‐purposeprocessorstomanipulatedata.
Thisexaminesdesignalternativesforbarrelshiftersthatperformthefollowingfunctions:
Shiftrightlogical,shiftrightarithmetic,rotateright,shiftleftlogical,shiftleftarithmetic,androtateleft.Fourdifferentbarrel
shifter designs are presented and compared in terms of area and delay for a variety of operand sizes. This also examines
techniquesfordetectingresultsthatoverflowandresultsofzeroinparallelwiththeshiftorrotateoperation.
1. INTRODUCTION
arithmetic and shift left arithmetic operations. An n‐bit
logarithmicbarrelshifteruseslog2(n)stages[1,2].Each
bitoftheshiftamount,B,controlsadifferentstageofthe
shifter.Thedataintostagecontrolledbybkisshiftedby
2kbitsifbk=1;otherwiseitisnotshifted.Techniquesare
also presented for detecting results that overflow and
results of zero in parallel with the shift or rotate
operation.
A barrel shifter is a digital circuit that can shift a data
wordbyaspecifiednumbersofbitsinoneclockcycle.It
can be implemented as a sequence of multiplexors
(mux),andinsuchanimplementationtheoutputofone
muxisconnectedtothenextmuxinawaythatdepends
ontheshiftdistance.Barrelshiftersareoftenutilizedby
embeddeddigitalsignalprocessorsandgeneralpurpose
Tableno.‐1:Shiftandrotateexamplefor
processorstomanipulatedata.Shiftingandrotatingdata
A=a7a6a5a4a3a2a1a0andB=3
is required in several applications, variable‐length
coding, and bit indexing. The mux based barrel shifter
Operation
Y
architecture are designed using 4:1,8:1,16:1,32:1,and
64:1muxtrees.Eachmuxtreeisdesignedusing2:1mux.
3‐bitshiftrightlogical
000a7a6a5a4a3
The power consumed by mux trees is quite significant
andcannotbeignored.Thusitisimportanttominimize
3‐bitshiftrightarithmetic a7a7a7a7a6a5a4a3
power dissipation of mux trees within low power
designs.Multiplexersaredigitalcircuitthatgeneratesan
3‐bitrotateright
a2a1a0a7a6a5a4a3
output that exactly reflects state of one of a number of
datainputs,basedonvalueofselectlines.Amultiplexer
3‐bitshiftleftlogical
a4a3a2a1a0000
withtwodatainputandoneselectlineisreferredas“2‐
to‐1or 2:1”multiplexer. A barrel shifter primarily offers
3‐bitshiftleftarithmetic
a7a3a2a1a0000
fiveoperations;rotateright,rotateleft,shiftrightlogical,
shift left logical, and shift right arithmetic, shift left
3‐bitrotateleft
a4a3a2a1a0a7a6a5
arithmetic. An n‐bit logarithmic barrel shifter uses log2
(n)stages[1,2].Eachbitoftheshiftamount,B,controls
a different stage of the shifter. The data in to stage
3. DESIGNMETHODOLOGIES
controlledbybkisshiftedby2kbitsifbk=1;otherwiseit
is not shifted. Techniques are also presented for
Tools:‐Modelsim
detecting results that overflow and results of zero in
parallelwiththeshiftorrotateoperation.
BlockDiagram:‐
2. DESIGNSPECIFICATION
Basic shifter and rotator designs are described first
followedbyMux‐baseddata‐reversalbarrel‐shifters.The
term multiplexer refers to a 1‐bit to 2‐to‐1 multiplexor
unlessotherwisestated.Arowofnmultiplexorsreverse
the order of the data when left=1 to produce the final
result. A Mux based data reversal barrel shifter, also
detectoverflowandresultsofzero.Overflowonlyoccurs
when performing a shift left arithmetic operation and
one or more of the shifted‐out bits differ from the sign
bit. The operation performed by the barrel shifters is
controlled by a 3‐bit opcode, which consists of the bits
left, rotate and arithmetic, additional control signal, sra
and sla are set to one when performing shift right
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PRAGATI SACHAN et al.
DATE OF PUBLICATION: SEP 23, 2014
ISSN: 2348-4098
VOLUME 2 ISSUE 7 SEP-OCT 2014
TheblockdiagramshowingtheDatain,direction,input
reversal,shiftorrotate,selectline,outputreversal,data
out.
TableNO.–2:BarrelShifterFunctionality
3.1Operationcontrolbit
1. A B‐bit shift right logical operation performs a B‐bit
rightshiftandsetstheupperBbitsoftheresulttozeros.
Mode
Rotation Direction
Description
2.AB‐bitshiftrightarithmeticoperationperformsaB‐
bit right shift and sets the upper B bits of the result to
an‐1,whichcorrespondstothesignbitofA.
Shift
Left
Logical
0
0
Logicshiftleft,0is
shifted through
the right most
(lsb)bit.
3. A B‐bit rotate right operation performs a B‐bit right
shiftandsetstheupperBbitsoftheresulttothelowerB
bitsofA.
Rotate
Left
1
0
Left rotate, the
right most bit is
shifted back in
formtheright.
Shift
Right
Logical
0
Rotate
Right
1
1
1
Logical shift right,
0isshiftedtheleft
most(msb)bit.
Right rotate, the
right most bit is
back in from the
left.
The right rotator and the logical right shifter supply
different inputs to the more significant multiplexors.
Withtherotator,sincealloftheinputbitsareroutedto
the output, there is no longer a need for interconnect
lines carrying zeros. Instead, interconnect lines are
insertedto enable routingofthe 2k loworderdata bits
tothe2khighordermultiplexorsinthestagecontrolled
bybk.Changingfromanon‐optimizedshiftertoarotator
has no impact on the theoretical area or delay. The
longer interconnect lines of the rotator; however, can
increasebothareaanddelay.Thelogicalrightshiftercan
be extended to also perform shift right arithmetic and
rotate right operations by adding additional
multiplexors.Thisforan8‐bitrightshifter/rotatorwith
three stages of 4‐bit, 2‐bit, and 1‐bit shifts/rotates.
Initially, a single multiplexor selects between '0' for
logicalrightshiftingand1forarithmeticrightshiftingto
produces.Inthestagecontrolledbybk,2kmultiplexors
selectbetweensforshiftingandthe2klowerbitsofthe
dataforrotating.Beforeandaftertherightshifter,when
a left shift operation is performed, these multiplexors
reversethedataintoandoutoftherightshifter.Whena
rightshiftoperationisperformed,thedataintoandout
oftheshifterisnotchanged.
Tableno3
4.AB‐bitshiftleftlogicaloperationperformsaB‐bitleft
shiftandsetsthelowerBbitsoftheresulttozeros.
5.AB‐bitshiftleftarithmeticoperationperformsaB‐bit
leftshiftandsetsthelowerBbitsoftheresulttozeros.
Thesignbitoftheresultissettoan‐1.
6.AB‐bitrotateleftoperationperformsaB‐bitleftshift
andsetsthelowerBbitsoftheresulttotheupperBbits
ofA.
The operation performed by the barrel shifters is
controlled by a 3‐bit opcode, which consists of the bits
left, Rotate, and arithmetic, as summarized in Table 3.
Additional control signals, sra and sla, are set to one
when performing shift right arithmetic and shift left
arithmeticoperations,respectively.
4. DESIGNIMPLEMENTATION
Abarrelshifterisoftenimplementedasa:‐
RotateandShiftDirection:‐Thedirectionoftherotate
and shift operation is implemented by reversing the
inputandoutputvector,usingthismethodallowsforthe
shiftorrotatelogictobekeptsimple.
[A]LogicalShiftOperation:‐Thelogicalshiftoperation
inserts0valuesforeachshiftoperation.Theinputvector
is shifted in the selected direction according to the
numberofbitsintheselectindication.
[B] Rotate Operation: ‐ The rotate operation is a shift
where the bit which is shifted out of the vector MSB is
insertedatitsLSB.
[C] Shift and Rotate Operation: ‐ We defined A to be
theinputoperand,Btobetheshift/rotateamount,andY
INTERNATIONAL JOURNAL OF SCIENCE, ENGIEERING AND TECHNOLOGY- www.ijset.in
1435
PRAGATI SACHAN et al.
DATE OF PUBLICATION: SEP 23, 2014
ISSN: 2348-4098
VOLUME 2 ISSUE 7 SEP-OCT 2014
tobetheshifted/rotatedresult.WedefineAtobeann‐
bitvalue,wherenisanintegerpoweroftwo.Therefore,
Bisalog2(n)‐bitintegerrepresentingvaluesfrom0ton
‐ 1 we define A to be the input operand, B to be the
shift/rotate amount, and Y to be the shifted/rotated
result. We define A to be an n‐bit value, where n is an
integer power of two. Therefore, B is a log2(n)‐bit
integerrepresentingvaluesfrom0ton‐1.
4.1.Figure1‐8‐Bitlogicalrightshifter
4.2.Figure2‐8Bitrightrotator
Figure1showstheblockdiagramofan8‐bitlogicalright
shifter, which uses three stages with 4‐bit, 2‐bit, and 1‐
bit shifts. To optimize the design, each multiplexor that
has'0'foroneofitsinputscanbereplacedbya2‐input
andgatewiththedatabitandbkasinputs.Asimilarunit
thatperformsrightrotations,insteadofrightshifts,can
be designed by modifying the connections to the more
significant multiplexors. Figure 2 shows the block
diagramofan8‐bitrightrotatorwhichusesthreestages
with4‐bit,2‐bit,and1‐bitrotates.Therightrotatorand
the logical right shifter supply different inputs to the
moresignificantmultiplexors.Withtherotator,sinceall
of the input bits are routed to the output, there is no
longer a need for interconnect lines carrying zeros.
Instead,interconnectlinesareinsertedtoenablerouting
of the 2k low order data bits to the 2k high order
multiplexors in the stage controlled by bk. Changing
fromanon‐optimizedshiftertoarotatorhasnoimpact
onthetheoreticalareaordelay.Thelongerinterconnect
linesoftherotatorcanincreasebothareaanddelay.The
logicalrightshiftercanbeextendedtoalsoperformshift
right arithmetic and rotate right operations by adding
additional multiplexors. This approach is illustrated in
Figure 3, for an 8‐bit right shifter/rotator with three
stages of 4‐bit, 2‐bit, and 1‐bit shifts/rotates. Initially, a
single multiplexor selects between '0' for logical right
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PRAGATI SACHAN et al.
DATE OF PUBLICATION: SEP 23, 2014
ISSN: 2348-4098
VOLUME 2 ISSUE 7 SEP-OCT 2014
shiftingandan‐1forarithmeticrightshiftingtoproduce
s. In the stage controlled by bk, 2k multiplexors select
between s for shifting andthe 2k lowerbits of the data
forrotating.
4.3Figure3‐8Bitdatareversal
5. SIMULATIONANDRESULTS
5.1.SimulationResult(rightshift)
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PRAGATI SACHAN et al.
DATE OF PUBLICATION: SEP 23, 2014
ISSN: 2348-4098
VOLUME 2 ISSUE 7 SEP-OCT 2014
5.2.SimulationResult(leftshift)
5.3.SimulationResult(reversal)
5.4.SimulationResult(rotator)
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PRAGATI SACHAN et al.
DATE OF PUBLICATION: SEP 23, 2014
ISSN: 2348-4098
VOLUME 2 ISSUE 7 SEP-OCT 2014
5.5.SimulationResult(shift+rotateright)
5.6.SimulationResult(shifts+rotatesleft)
5.7.SimulationResult(barrelshifter)
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PRAGATI SACHAN et al.
DATE OF PUBLICATION: SEP 23, 2014
ISSN: 2348-4098
VOLUME 2 ISSUE 7 SEP-OCT 2014
6. FUTUREEXPECTS
The future expects of barrel shifter is that it minimize
the area and power delay of the circuit. Area and delay
estimates, based on synthesis of structural level VHDL,
indicatethatdata‐reversalbarrelshiftershavelessarea
than two's complement or one's complement barrel
shifters and that mask‐based data‐reversal barrel
shifters have less delay than the other designs. As the
operandsizeincreases,thedelayoftheshiftersincreases
asO(log(n))andtheirareaincreasesasO(nlog(n)).Into
the future expectation we attach a overflow detection
logic,sothedatashouldnotbewaste.
7. CONCLUSION
This paper named “Barrel Shifter” undertook by the
studentofM.Tech(VERILARGESCALEINTEGERATION)
THIRD SEMESTER under the guidance and support of
ourteacher.
The reason behind undertaking this project simply lies
with the fact that there are so many circuits that have
morepowerconsumptionanddelay,sotominimizethe
areaanddelayweareusingshiftingorrotation.Herewe
aredoingshiftrightlogical,shiftrightarithmetic,rotate
right,shiftleftlogical,shiftleftarithmetic,androtateleft.
Four different barrel shifter designs are presented and
compared in terms of area and delay for a variety of
operand sizes. This is also examines techniques for
detecting results that overflow and results of zero in
parallelwiththeshiftorrotateoperation.
Toresolvethispurposewehavemadethisveryproject,
so that if such a kind of system is used then at least it
may be able to sense the shifting or rotation and
accordinglynecessaryconditionscanbeundertaken.
REFERENCES
1.www.realwordtech.com.
2.BarrelShifterorMultiply/DivideICStructure.
3.CircuitforRotating,LeftShifting,orRightShiftingBits.
4.MultilevelBarrelShifterforCORDICDesign.
5.High‐SpeedBarrelShifter.
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