Problem Set 7

Introduction to Computer Engineering (E114)
Harris
Spring 1999
Problem Set 7
Due: Friday, March 26
Reading: Chapter 5.1-5.4, Appendix C1-C3
1) Adding Instructions to a Single-Cycle Processor
Ben Bitdiddle needs the lui instruction for his MIPS processor. Extend the single-cycle
processor from Section 5.3 to handle lui. Attached is Figure 1 showing the single-cycle
datapath. If you need to modify the datapath, mark your modifications on the figure. If
not, leave the figure unmarked. Then add a row to the table below showing control
signals that must be asserted. If you need any additional control signals, add another
column to the table.
Control Outputs
Op[5:0]
Instruction
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
Jump
ALUOp[1:0]
000000
R-type
1
0
0
1
0
0
0
0
10
100011
lw
0
1
1
1
1
0
0
0
00
101011
sw
X
1
X
0
0
1
0
0
00
000100
beq
X
0
X
0
0
0
1
0
01
000010
j
X
X
X
0
0
0
0
1
00
lui
Page 1 of 3
0
M
u
x
Add
Add
RegDst
Branch
MemRead
4
Instruction [31 26]
Read
address
Instruction
memory
Instruction [15 11]
PCSrc
Read
register 1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
Instruction [20 16]
Instruction
[31– 0]
1
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Control
Instruction [25 21]
PC
ALU
result
Shift
left 2
0
M
u
x
1
Zero
ALU ALU
result
0
M
u
x
1
Write
data
Write
data
16
Instruction [15 0]
Sign
extend
Read
data
Address
Data
memory
1
M
u
x
0
32
ALU
control
Instruction [5 0]
Figure 1: Single-Cycle Datapath
2) Adding Instructions to a Multi-Cycle Processor
Now Ben would also like to use the lui instruction in his multi-cycle MIPS processor.
Extend the multi-cycle processor from Section 5.4 to handle lui. Attached is Figure 2
showing the multi-cycle datapath. If you need to modify the datapath, mark your
modifications on the figure. Then change the Finite State Machine in Figure 3 to produce
the required control signals at the right times.
PCWriteCond
PCSource
PCWrite
ALUOp
Outputs
IorD
ALUSrcB
MemRead
ALUSrcA
Control
MemWrite
RegWrite
MemtoReg
IRWrite
Op
[5– 0]
RegDst
0
M
26
Instruction [25– 0]
PC
0
M
u
x
1
Shift
left 2
Instruction
[31-26]
Instruction
[25– 21]
Address
Memory
MemData
Write
data
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Instruction
[20– 16]
Instruction
[15– 0]
Instruction
register
Instruction
[15– 0]
Memory
data
register
0
M
Instruction u
x
[15– 11]
1
A
B
4
Write
data
0
M
u
x
1
16
Sign
extend
32
Instruction [5– 0]
Figure 2: Multi-Cycle Datapath
Page 2 of 3
ALU
control
1 u
x
2
Zero
ALU
0
1 M
u
2 x
3
Shift
left 2
Jump
address [31-0]
PC [31-28]
0
M
u
x
1
Read
register 1
28
ALU
result
ALUOut
Instruction decode/
register fetch
Instruction fetch
( Op
2
or
W')
= 'L
( Op
EQ
')
)
Branch
completion
Execution
6
e
-typ
=R
'B
(O p
W')
= 'S
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
8
ALUSrcA =1
ALUSrcB = 00
ALUOp = 10
Jump
completion
9
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSource = 01
PCWrite
PCSource = 10
(O
p
=
'S
')
W
(Op = 'LW')
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
(Op = 'J')
Memory address
computation
1
=
Start
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
PCWrite
PCSource = 00
(O
p
0
Memory
access
3
Memory
access
5
MemRead
IorD = 1
R-type completion
7
MemWrite
IorD = 1
RegDst = 1
RegWrite
MemtoReg = 0
Write-back step
4
RegDst = 0
RegWrite
MemtoReg = 1
Figure 3: Multi-Cycle Control
3) Time
Please indicate how many hours you spent on this problem set. This will not affect your
grade, but will be helpful for calibrating the workload for next semester’s class.
Page 3 of 3

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