presentation

Brno University of Technology
Interrupts
Microprocessor Techniques and Embedded Systems
Lecture 4
Dr. Tomas Fryza
Ver. 2014-10-21
Contents
Interrupt Routines
External Interrupts
Timer/Counter
Source Code Example for ATmega16 – Interrupt Request
Contents
Interrupt Routines
External Interrupts
Timer/Counter
Source Code Example for ATmega16 – Interrupt Request
Interrupt Requests
I
The program execution (or more precisely PC value) could be effected also by
so called interrupts.
I
While the CPU received the (enabled) interrupt request, it stops executing the
main code and starts to run the specific interrupt routine. (This routine is unique
for every interrupt source.)
I
Each microcontroller contains a set of possible interrupts (internals, externals)
which correspond to hardware structure and to available peripheries.
I
Each interrupt source is connected to single interrupt vector, which is an unique
address in program memory, where routines have to be located.
I
Each interrupt have to be enabled. In addition there is a global interrupt enable
(I-bit in SREG).
Remq.: Each interrupt has its own priority: the lower interrupt vector, the higher priority
(see next page).
Interrupt Vectors of ATmega16
Vector No.
Address
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0012
0x0014
0x0016
0x0018
0x001A
0x001C
0x001E
0x0020
0x0022
0x0024
0x0026
0x0028
*.inc
INT0addr
INT1addr
OC2addr
OVF2addr
ICP1addr
OC1Aaddr
OC1Baddr
OVF1addr
OVF0addr
SPIaddr
URXCaddr
UDREaddr
UTXCaddr
ADCCaddr
ERDYaddr
ACIaddr
TWIaddr
INT2addr
OC0addr
SPMRaddr
Source
Interrupt Description
RESET
INT0
INT1
TIMER2 COMP
TIMER2 OVF
TIMER1 CAPT
TIMER1 COMPA
TIMER1 COMPB
TIMER1 OVF
TIMER0 OVF
SPI, STC
USART, RXC
USART, UDRE
USART, TXC
ADC
EE RDY
ANA COMP
TWI
INT2
TIMER0 COMP
SPM RDY
External Pin, Power-on Reset, ...
External Interrupt Request 0.
External Interrupt Request 1.
Timer/Counter2 Compare Match.
Timer/Counter2 Overflow.
Timer/Counter1 Capture Event.
Timer/Counter1 Compare Match A.
Timer/Counter1 Compare Match B.
Timer/Counter1 Overflow.
Timer/Counter0 Overflow.
Serial Transfer Complete.
USART, Rx Complete.
USART Data Register Empty.
USART, Tx Complete.
ADC Conversion Complete.
EEPROM Ready.
Analog Comparator.
Two-wire Serial Interface.
External Interrupt Request 2.
Timer/Counter0 Compare Match.
Store Program Memory Ready.
Interrupt Vectors of ATtiny11
Vector No.
Address
1
2
3
4
5
0x000
0x001
0x002
0x003
0x004
Source
Interrupt Description
RESET
INT0
I/O piny
TIMER0 OVF
ANA COMP
External Pin, Power-on Reset, . . .
External Interrupt Request 0.
Pin Change Interrupt.
Timer/Counter0 Overflow.
Analog Comparator.
I
See addresses between neighbouring vectors for ATtiny and ATmega devices –
not enough space for whole routine. Standard practice is to put here only the
jump to separate routine.
I
After the interrupt execution, the PC returns back to precedent place (when
interrupt request come). I.e. the stack for return addresses storing is needed
(similar to subroutines).
Remq.: ATtiny 11 device does not have a SRAM data memory, therefore the hardware
stack for three addresses is included.
Remq.: ATtiny 11 has 1kB Flash memory.
Interrupt Handling
I
When interrupt request is occurred:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
I
the currently executing instruction is completed,
other interrupt requests are disabled,
storing of return address to stack (that’s why stack has to be already defined),
filling of PC by concrete interrupt vector address (e.g. for external interrupt 0 in
ATmega16: PC=0x0002),
executing of interrupt routine,
return from interrupt by RETI instruction (analogy to return from subroutine),
all others interrupts are enabled,
loading of return address from stack to program counter,
continuing of main code execution.
Similar to subroutines, the stack memory must be defined/configured in advance.
Just once, at the beginning of the main application.
Help: reti
I
Return from Interrupt.
I
No parameter.
I
Programmer point of view: go back from the last insterrupt service routine. CPU
point of view: read the last return address from the top of the stack and copy it
to Program Counter.
External Interrupts – example
Figure: Sources for external interrupts for ATmega16.
I
In ATmega16 the External Interrupts are triggered by the INT0, INT1, and INT2
pins.
External Interrupts – example
I
Interrupt routine would be executed if:
(1) external interrupt is enabled via GICR register,
7
6
5
4
3
2
1
0
INT1
INT0
INT2
−
−
−
IVSEL
IVCE
GICR
Figure: Structure of GICR (General Interrupt Control Register).
(2) SREG I-bit is set (global interrupt enable).
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
SREG
Figure: Structure of SREG (Status Register) for AVR microcontrollers.
I
The external interrupts can be triggered by a falling or rising edge or a low level;
see control register MCUCR (MCU Control Register).
7
6
5
4
3
2
1
0
SM2
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
Figure: Structure of MCUCR (MCU Control Register).
MCUCR
Setting of external interrupts
Table: Interrupt ”n” sense control (register MCUCR).
ISCn1:0
0b00
0b01
0b10
0b11
Description
The
Any
The
The
low level of INT1 or INT0 generates an interrupt request.
logical change on INT1 or INT0 generates an interrupt request.
falling edge of INT1 or INT0 generates an interrupt request.
rising edge of INT1 or INT0 generates an interrupt request.
Example
Fill the MCUCR control register by specific byte, if the generation of external interrupt
INT1 is requested. Let a rising edge triggers the interrupt.
7
6
5
4
3
2
1
0
SM2
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
Figure: Structure of MCUCR (MCU Control Register).
MCUCR
Example: External Interrupt Routine in Assembly Language
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
.include <m16def_mod.inc>
.cseg
.org 0 x0000
rjmp reset
.org INT1addr
rjmp int1_routine
;
;
;
;
;
;
d e f i n i t i o n f i l e f o r ATmega16
F l a s h se gme nt
RESET h a n d l e r
jump t o r e s e t l a b e l
INT1 h a n d l e r
jump t o i n t 1 r o u t i n e l a b e l
.org I N T _ VECTORS_SIZE
reset :
; stack d e f i n i t i o n
ldi
R16 , low ( RAMEND )
ou t SPL , R16
ldi
R16 , h i g h ( RAMEND )
ou t SPH , R16
; s t o r e main c o d e from a d d r e s s 0 x002A
; interrupt (s) settings
ldi
R16 , (1<<INT1 )
; e n a b l e INT1
ou t GICR , R16
ldi
R16 , (1<<ISC11 ) |(1<<ISC10 )
ou t MCUCR , R16
; r i s i n g edge t r i g g e r s the i n t e r r u p t
sei
; set global interrupt
flag
loop :
rjmp loop
; f o r e v e r loop
; jump t o l o o p l a b e l
int1_routine :
...
reti
; interrupt routine start
; r e t u r n from i n t e r r u p t
Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on
page 83. of Timer/Counter
Block diagram
Figure 27. 8-bit Timer/Counter Block Diagram
TCCRn
count
TOVn
(Int.Req.)
clear
Control Logic
direction
clk Tn
Clock Select
Edge
Detector
DATABUS
BOTTOM
Tn
TOP
( From Prescaler )
Timer/Counter
TCNTn
=
=0
= 0xFF
OCn
(Int.Req.)
Waveform
Generation
OCn
OCRn
The
Timer/Counter
(TCNT0)
Output Compare
(OCR0)
are 8-bit registers.
Figure:
Block diagram
of and
Timer/Counter
(”n” Register
represents
timer/counter
index).
Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer
Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since
these registers are shared by other timer units.
mer/Counter Timing
agrams
on when Interrupt Flags are set. Figure 34 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
The
is a PWM
synchronous
otherTimer/Counter
than phase correct
mode. design and the timer clock (clkT0) is therefore
shown as a clock enable signal in the following figures. The figures include information
on
when
Interrupt
Flags
are
set.
34 contains
timing data for basic Timer/Counter
Figure 34. Timer/Counter TimingFigure
Diagram,
no Prescaling
1
operation. The figure shows the count sequence
close to the MAX value in all modes
tOVF
· N · 2n
other than phase correct PWM
mode.=
Timer/Counter prescaler
f
CPU
clkI/O
Figure 34. Timer/Counter Timing Diagram, no Prescaling
clkTn
(clk
clkI/O/1)
I/O
TCNTn
clkTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
MAX - 1
MAX
BOTTOM
BOTTOM + 1
(clkI/O /1)
TOVn
TCNTn
TOVn35 shows the same timing data, but with the prescaler enabled.
Figure
Figure 35. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
Figure 35 shows the same timing data, but with the prescaler enabled.
clkI/O
Figure 35. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkTn
(clkI/O /8)
clkI/O
TCNTn
clkTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
MAX - 1
MAX
BOTTOM
BOTTOM + 1
(clkI/O /8)
TOVn
TCNTn
TOVn36 shows the setting of OCF0 in all modes except CTC mode.
Figure
Figure: Counting with no prescaler and prescaler N = 8.
(1)
Contents
Interrupt Routines
External Interrupts
Timer/Counter
Source Code Example for ATmega16 – Interrupt Request
Example: Interrupt Routine in Assembly Language
I
While interrupts or subroutines are used, the stack has to be defined.
I
Common practice in microprocessor techniques: main program ends with forever
loop and all routines are programmed by interrupts.
Interrupt vectors used in example:
I
I
I
I
0x0000 – RESET,
0x0002 – External Interrupt Request 0,
0x001C – ADC Conversion Complete.
Example: Interrupt Routine in Assembly Language
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
.include <m16def_mod.inc>
.org 0 x0000
rjmp reset
.org INT0addr
rjmp btn_press
.org ADCCaddr
rjmp ad_conv
; main a p p l i c a t i o n
.org I N T _ VECTORS_SIZE
reset :
...
...
sei
;
;
;
;
;
;
;
d e f i n i t i o n f i l e f o r ATmega16
RESET h a n d l e r
jump t o r e s e t l a b e l
INT0 h a n d l e r
jump t o b t n p r e s s l a b e l
ADC h a n d l e r
jump t o a d c o n v l a b e l
; s t o r e main c o d e from a d d r e s s 0 x002A
; stack d e f i n i t i o n
; interrupt (s) settings
; set global interrupt
flag
loop :
rjmp loop
; f o r e v e r loop
; jump t o l o o p l a b e l
btn_press :
...
reti
; i n t e r r u p t r o u t i n e f o r INT0
ad_conv :
...
reti
; r e t u r n from i n t e r r u p t
; i n t e r r u p t r o u t i n e f o r ADC
; r e t u r n from i n t e r r u p t

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