Nanoscopic Study of HfO2 Based HK Dielectric Stacks and Its

International Journal of Materials Science and Engineering Vol. 2, No. 2 December 2014
Nanoscopic Study of HfO2 Based HK Dielectric
Stacks and Its Failure Analysis
K. Shubhakar
Singapore University of Technology and Design, 20 Dover Drive, Singapore 138682
Division of Microelectronics, School of Electrical and Electronic Engineering, Nanyang Technological University, 50
Nanyang Avenue, Singapore 639798
Email: [email protected]
N. Raghavan and K. L. Pey
Singapore University of Technology and Design, 20 Dover Drive, Singapore 138682
Email: {Nagarajan.raghavan, peykinleong}@sutd.edu.sg
Abstract—In this invited paper, we present local electrical
characteristics, degradation phenomenon and breakdown
analysis of polycrystalline HfO2 dielectric stacks at
nanometer scale resolution. Grain boundaries (GBs) in
polycrystalline high-κ (HK) dielectric films play a major
role in the performance and reliability metrics of HK based
advanced metal-oxide-semiconductor (MOS) devices. Hence,
it is important to study the degradation and breakdown
phenomenon in polycrystalline HfO2 dielectric stacks. The
nanoscale localized dielectric breakdown (BD) events are
analysed using conductive-atomic force microscopy (C-AFM)
and transmission electron microscopy (TEM) techniques.
Results show an enhanced trap generation and faster
degradation of polycrystalline HfO2 gate dielectrics at GB
sites as compared to the bulk (grain) regions. A new
technique is adopted to induce the degradation and BD of
the HfO2 dielectric locally using a combined scanning
tunnelling microscopy/scanning electron microscopy nanoprobing system. This method of analysis is very useful in
studying the nature of the breakdown events in dielectrics,
elucidating the structural changes of the dielectric and the
role of the gate electrode in dielectric BD events.
resolution [6]-[9]. Again, identification of the BD
locations is one of the major issues in the study of failure
analysis of MOSFETs. Therefore, special techniques to
identify and analyse the BD sites at a nanometer
resolution are required to investigate the nature of
localized degradation and BD of the dielectric in detail.
Here we demonstrate the combined study of conductiveAFM (C-AFM) and the transmission electron microscopy
(TEM) analysis of the degradation and BD in nanometer
resolution.
II.
In this work, C-AFM has been used to characterize the
morphology and local electrical properties of HfO 2/SiOx
dielectric stack. AFM experiments were carried out in
ultra-high vacuum (~10–10 Torr). The conducting Pt-wire
AFM tip (apex diameter ~50nm) acts as a top gate
measures the leakage current across the dielectric at every
pixel while scanning for the topographical image, with a
constant voltage bias applied to the sample. The tip was
always grounded while a bias was applied to the sample.
Hence, the topographical and electrical properties of the
dielectric can be collected simultaneously at a nanometer
scale. Current-stress time (I-t) studies were also carried
out at different locations on the polycrystalline HfO 2
dielectric. Annealed (600°C) HfO2 (~4nm)/SiOx
(~1nm)/Si samples, which were fabricated using atomic
layer deposition technique, were used. A technique that
combines scanning electron microscopy (STM) and
scanning electron microscopy (SEM) with nano-probing
facility was also used in our work to induce the localized
BD on HfO2/SiOx dielectric stack. Electron-beam
patterned Au (~80nm)/Ti (~5nm) gate electrodes were
fabricated on HfO2/SiOx dielectric stacks and these
devices were subjected to a STM tip induced ramped
voltage stressing (RVS) for the BD events under constant
height mode STM operation. This was followed by
focused ion-beam sample preparation to carry out TEM
analysis. Fig. 1 shows the cross-sectional TEM
micrographs of metal/HfO2 (~5nm)/SiOx (~1nm)/Si
structure.

Index Terms—dielectric, grain
conductive-AFM, breakdown
I.
boundary,
high-κ,
INTRODUCTION
The degradation and failure of high-κ (HK) dielectrics
would be a major challenge for the reliability of HKbased CMOS technology. In MOS structures, the
conventional electrical tests at device level do not provide
the complete physical analysis of the localized
percolation path formation and subsequent breakdown
(BD) events in dielectrics. The formation of the
conductive percolation path and eventual dielectric BD
events are localized [1]-[7]; it is therefore essential to
study these phenomena with nanometer resolution to
analyse the overall reliability and failure of advanced HK
gate dielectric stacks. Atomic force microscopy (AFM)
technique is used extensively as a tool for the
characterization of HK dielectrics with nanometer
Manuscript received November 11, 2013; revised February 15, 2014.
©2014 Engineering and Technology Publishing
doi: 10.12720/ijmse.2.2.81-86
EXPERIMENTS
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International Journal of Materials Science and Engineering Vol. 2, No. 2 December 2014
Figure 1. Cross-sectional TEM micrograph of HfO2 (~4nm)/SiO2 (~1nm)
on Si-substrate, annealed at 600°C, showing the polycrystalline HfO2
dielectric.
III.
Figure 3. Weibull plot of TDDB for C-AFM induced BD locations
(~20) in the HfO2/SiOx stack [7].
RESULTS AND DISCUSSIONS
A. HfO2 Dielectric Degradation and Breakdown
Analysis
There are a few reports relating to higher leakage
current at the GB sites of polycrystalline HfO2 dielectrics
[10]-[13]. Grain boundaries (GBs) in polycrystalline HK
dielectrics contain a high density of defects which
favoring an accumulation of more traps, leading to the
formation of a percolation path [10], [11]. We directly
address this issue using C-AFM experiments and
simulations in this section.
Fig. 2(a) and Fig. 2(b) show a C-AFM topographical
image and the corresponding current map, showing the
grains and their GB contours. A higher leakage current,
i.e., bright spots on the current map at the GB locations,
was observed corresponding to the depressed locations on
the topographical image, indicating the enhanced trapassisted tunneling (TAT) through the high concentration
of pre-existing traps present at the GBs [10]-[12]. Fig. 2(c)
shows a line profile of the topography and current map
along the line X1-X2 depicting an increase in the leakage
current at the GB locations.
Figure 4. Simulated failure time distribution for (a) amorphous and (b)
polycrystalline HK thin film of thickness. Higher localized trap
generation rate at the GB causes the distribution to be non-Weibull [14].
A localized leakage current evolution with stress time
under constant voltage stressing (CVS) of +6V, at
different locations (grain and GB regions), was
performed. During the CVS test, the C-AFM tip was
maintained over a location for a specific period of time
with a constant voltage applied between the tip and the
sample. Fig. 3 shows the Weibull probability plot of the
time-dependent
dielectric
breakdown
(TDDB)
distribution for C-AFM induced localized BD events of
HfO2/SiOx dielectric stack at ~20 different locations. The
results clearly show a convexial distribution, with steeper
low percentile and shallower high percentile trends [7].
This non-linearity is more likely due to the GB defects
present in the HK dielectric. The Weibull plots of
simulated (Kinetic Monte Carlo) time-to-failure (TTF)
distribution for an amorphous and polycrystalline HfO2
film are used to analyse the failure distribution in HK
dielectrics. Fig. 4 shows the simulated time to failure
(TTF) distribution for an (a) amorphous and (b)
polycrystalline HfO2 film (with κGB = 26 (dielectric
constant at GB region) > κG = 25 (dielectric constant at
grain region)) [14]. The amorphous stack shows a linear
trend in the Weibull scale clearly representative of the
standard Weibull distribution (Fig. 4(a)). However, the
polycrystalline microstructure shows convexial trends
(Fig. 4(b)) with steeper low percentile and shallower high
percentile trends [14]. Since the only parameter change in
these two cases is κGB ≠ κG, it can be implied that non-
Figure 2. (a) C-AFM topography, (b) corresponding C-AFM current
map (at +5V) of HfO2 gate dielectric depicting the grain and GB profile.
(c) Line profile of topography and C-AFM current map along line “X1X2” shown in (a) and (b).
©2014 Engineering and Technology Publishing
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International Journal of Materials Science and Engineering Vol. 2, No. 2 December 2014
The nanometer scale C-AFM results correlate well
with the GB assisted BD phenomenon evidence in device
level HfO2/SiOx dielectric stacks as shown in Fig. 7 [15].
Bright contrast lines along the GB region in the TEM
cross-section of the failed NMOS device is clearly
observed along with dielectric breakdown induced
epitaxy (DBIE) microstructural defects, pointing to the
preferential occurrence of failures at the proximity of the
GB site [15]. Fig. 8 shows the schematics of higher
electric field at IL below the GB, GB degradation effect
on IL and its breakdown phenomenon.
uniform localized trap generation leads to the convexial
TTF distribution trends. The extent of defectivity in the
GB therefore plays a major role in governing the shape of
the statistical distribution [14]. Weibull plot of TDDB for
C-AFM data is in good agreement with the simulation
results.
The impact of uniform electrical stress was analyzed
on polycrystalline HfO2 dielectric using C-AFM. Fig. 5(a)
and Fig. 5(b) show the topography and current map in the
first scan obtained at +6V, respectively. Fig. 5(c) and Fig.
5(d) show the current maps over the same area in the
second and third scans, respectively, obtained at +6V.
The magnitude of the leakage current and conducting
region along the GB increases upon uniform stressing,
indicating a higher rate of stress induced trap generation
compared to the grain regions. Fig. 6 shows the line
profile of topography and current maps along the line “XY” in Fig. 5. Results clearly indicate higher increase in
the leakage current and faster degradation along the GBs
upon stressing.
Hence, these conductive percolation paths could
evolve into BD spots. Underlying the GB, the thin SiOx
interfacial layer (IL) region experiences enhanced local
electric field due to a lower electrical resistance in the GB
path, causing stress-induced traps to be generated within
the IL, resulting in the degradation and BD of the IL layer,
which could further enhance the degradation rate locally
at that particular GB location [7].
Figure 7. TEM cross-section of a GB site failure in the HfO2 HK layer
along with DBIE [15]
Figure 8. Schematics of the proposed BD sequence in HK/IL dielectric
stack. (a) Higher electric field at IL below the GB (rectangular box in
yellow), (b) further increased electric field at IL below the degraded GB
upon stressing (rectangular box in red), and (c) IL BD in HK/IL
dielectric stack (small circles represent the traps in the dielectric) [7].
To induce a localized BD in tip injection mode, a
specific location on the HfO2 dielectric was selected and
subjected to localized stressing by maintaining the
conductive AFM tip at a location with a bias applied
between tip and sample. The C-AFM topographic (Fig.
9(a)-(c)) and corresponding current images (Fig. 9(d)-Fig.
9(f)), show the evolution of a localized BD event. Fig. 9(a)
and Fig. 9(d) show the C-AFM topography and current
image (at +6V) of the HfO2/SiOx dielectric stack,
respectively, before stressing. A location on the HfO2
dielectric marked in dotted circle was subjected to a CVS
at +7V (tip injection) locally until the BD event occurred.
Fig. 9(b) and Fig. 9(e) show the topographic and current
images after the BD event, respectively. No topographical
change was observed at the stressed location, indicating
no structural deformation occurred during the BD event,
but the conductivity at the stressed location increased
significantly as observed in the current image (Fig. 9(e)).
Inducing further stressing at the same location leads to
significant structural changes and current at the BD spot.
The formation of the depression/void at the BD spot was
observed in the surface topography as shown in Fig. 9(c).
The field-induced rupture of the HfO2/SiOx dielectric
stack in the direction of electron wind could be the
possible reason for the formation of depression at the BD
spot. Fig. 9(f) shows the corresponding current image of
the hard-BD (HBD) spot presenting highly conductive
region (dotted circle in Fig. 9(f)) [6].
Figure 5. (a) C-AFM topography and leakage current profile at +6V
after the (b) 1stscan, (c) 2ndscan, (d) 3rd scan of a HfO2/SiOx sample [7].
Figure 6. The line profile of topography and corresponding line profile
of the current maps during uniform stressing along the line “X-Y”
shown in Fig. 5 [7]
©2014 Engineering and Technology Publishing
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International Journal of Materials Science and Engineering Vol. 2, No. 2 December 2014
11(b) and Fig. 11(c) show the high-resolution (HR)-TEM
and scanning TEM (STEM) micrographs of the BD
region marked in Fig. 11(a). The dielectric is still intact,
where no punch through was found. The migration of
Au/Ti gate electrode material occurs at the BD region due
to the dielectric breakdown induced metal migration [18],
[19], forming a low resistance path between the gate and
Si substrate triggering the failure of the device. A “ballshaped” capping layer was formed at the Si substrate and
it was observed that the ball-shaped capping layer
induced by BD was found to be composed of gate
electrode material as presented in an elemental mapping
in Fig. 11(d), obtained at a spot marked by a dot in the
capping layer (Fig. 11(c)) [6].
Figure 9. (a)-(c) C-AFM topography profile at different stages of
localized degradation and breakdown under tip injection. (a) and (d) are
pre-stress results. Images (d)-(f) are the corresponding current maps for
(a)-(c) at +6V. The inset of (c) is the line profile of the topography at the
BD area [6].
B. STM Tip Induced Localized BD Analysis
Most of the analysis of the BD phenomenon of
HfO2/SiOx dielectric stack in the literature is based on
device-level electrical analysis. Using C-AFM, we have
demonstrated an analysis of the localized dielectric BD
using topographical and current images. The lack of
understanding on the physical analysis of these C-AFM
induced BD is largely due to the several experimental
difficulties involved in identifying the BD locations and
isolating accurately after the C-AFM analysis to prepare
the sample containing these extremely local BD locations
for the physical analysis using TEM. Here, we present a
technique to induce degradation and BD of the of a
HfO2/SiOx dielectric stack locally using STM/SEM
system [16], [17], in association with the nano-probing
technique. The STM induced BD devices were identified
and prepared the FIB sample containing BD spot for the
physical analysis using TEM. Two devices were used for
STM tip induced BD events. The first device was
subjected to moderate BD (~2-3 orders of the initial
leakage current) and the second device for hard BD (i.e.
very high conductivity after the BD). Fig. 10 shows the
tip placed at Au/Ti gate electrode area on the HfO2
dielectric.
Figure 11. (a) Cross-sectional TEM micrograph of Au/Ti/HfO2/SiOx
stack showing BD event for stressing moderate BD hardness. (b) TEM
micrograph with high magnification and (c) STEM at the BD location
indicated by dotted rectangle in (a). (d) Elemental mapping at the
location highlighted by a dot at “ball-shaped” capping layer in (c)
indicating Au migration to the Si substrate at the BD site [6].
Fig. 12(a) and Fig. 12(b) show the cross-sectional
TEM of a non-BD and HBD devices, respectively. Fig.
12 (b) displays the catastrophic damage at the BD site
with the complete rupture of the dielectric stack, melting
and diffusion of gate electrode, and a burnt mark in Sisubstrate. The gate material melted with the creation of
high local temperature at the BD site due to the thermal
joule heating effect [18], [19].
Figure 10. SEM micrographs showing an STM tip placed on top of
Au/Ti/ HfO2/SiOx stack.
Figure 12. Cross-sectional TEM micrograph of (a) a non-BD location
and (b) hard-BD location, showing catastrophic failure of
Au/Ti/HfO2/SiOx stack. Rupture of HfO2/SiOx dielectric stack, Si
substrate melting, gate electrode melting and diffusion were observed at
the BD site.
Fig. 11(a) shows the TEM micrograph of the stressed
device containing the BD region (moderate BD). Fig.
©2014 Engineering and Technology Publishing
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International Journal of Materials Science and Engineering Vol. 2, No. 2 December 2014
IV.
[11] G. Bersuker, J. Yum, L. Vandelli, et al., “Grain boundary-driven
leakage path formation in HfO2 dielectrics,” Solid-State
Electronics, vol. 65, pp. 146-150, 2011.
[12] K. McKenna, A. Shluger, et al., “Grain boundary mediated
leakage current in polycrystalline HfO2 films,” Microelectron.
Eng., vol. 88, pp. 1272-1275, 2011.
[13] K. Shubhakar, K. L. Pey, et al., “Grain boundary assisted
degradation and breakdown study in cerium oxide gate dielectric
using scanning tunneling microscopy,” Appl. Phys. Lett., vol. 98,
pp. 072902(1-3), Feb. 2011.
[14] N. Raghavan, K. L. Pey, K. Shubhakar, X. Wu, W. H. Liu, and M.
Bosman, “Role of grain boundary percolative defects and
localized trap generation on the reliability statistics of high-κ Gate
dielectric stacks,” in Proc. IEEE International Reliability Physics
Symposium (IRPS), 2012, pp. 6A. 1.1-6A. 1.11.
[15] R. Ranjan, K. L. Pey, et al., “A comprehensive model for
breakdown mechanism in HfO2 high-k gate stacks,” in Proc. IEEE
International Electron Device Meeting (IEDM), 2004, pp. 725-728.
[16] A. Kaneko, Y. Homma, H. Hibino, and T. Oginoc, “Ultrahigh
vacuum scanning electron microscope system combined with
wide-movable scanning tunneling microscope,” Rev. Sci. Instrum.,
vol. 76, pp. 083709 (1-9), Aug. 2005.
[17] A. Wiessner, J. Kirschner, G. Schäfer, and T. Berghaus, “Design
considerations and performance of a combined scanning
tunnelling and scanning electron microscope,” Rev. Sci. Instrum.,
vol. 68, pp. 3790-3798, Jun. 1997.
[18] R. Ranjan, K. L. Pey, et al., “Substrate injection induced ultrafast
degradation in HfO2/TaN/TiN gate stack MOSFET,” in Proc.
IEEE International Electron Devices Meeting (IEDM), 2004, pp.
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SUMMARY
An analysis on the degradation and breakdown
phenomena was demonstrated at a very localized
nanometer scale breakdown location in a HfO2/SiOx
dielectric stack. Nanometer scale AFM analysis shows
higher variation of localized electrical properties and
morphology in polycrystalline HfO2. Therefore, the
microstructure of the HK thin film plays a critical role in
determining the TDDB robustness of advanced metal
gate-HK stacks and process optimization to control the
grain size and density distribution is bound to have a big
effect on future CMOS performance and lifetime
variability A combination of C-AFM and TEM can
become an effective approach to understand the physical
and electrical nature of failures in HK dielectric based
MOS devices.
ACKNOWLEDGEMENT
This work is supported by Singapore University of
Technology and Design (SUTD) Research Grant SRG
ASPE 2010 004, NTU Research scholarship and SUTDInternational Design Centre (IDC) Research Grant IDG
11300103.
REFERENCES
Kalya Shubhakar received his Ph.D. (2013)
from School of Electrical and Electronic
Engineering,
Nanyang
Technological
University (NTU), Singapore and M.Eng
(2007) in Microelectronics (Electrical
engineering Department) from Indian
Institute of Science (IISc), Bangalore, India.
He is currently working as a Senior Teaching
Fellow in Engineering Product Development
pillar at Singapore University of Technology
and Design (SUTD), Singapore. His main
research interests are in the nanoscale characterization and analysis of
high-κ date dielectrics for logic and memory devices. He was a
Graduate Student Member of IEEE (2010-2013).
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©2014 Engineering and Technology Publishing
Nagarajan Raghavan is currently pursuing
his Post Doctoral Fellowship at the
Singapore University of Technology and
Design (SUTD). Prior to this, he was a PostDoctoral Fellow at the Interuniversity
Microelectronics Center (IMEC) in joint
association with the Katholieke Universiteit
Leuven (KUL), Belgium. He obtained his
Ph.D. (Electronics Engineering, 2012) at the
Division of Microelectronics, Nanyang
Technological University (NTU), Singapore
and S.M. (Advanced Materials for Micro & Nano Systems, 2008) and
M.Eng (Materials Science and Engineering, 2008) from National
University of Singapore (NUS) and Massachusetts Institute of
Technology (MIT), Boston respectively.
His work focuses on statistical characterization and reliability modeling
of dielectric breakdown in novel high-κ dielectric materials. His other
research interests include random telegraph noise, prognostics for
nanodevices, design for reliability and reliability statistics.
Dr. Raghavan is the Asia-Pacific recipient for the IEEE EDS PhD
Student Fellowship in 2011 and the IEEE Reliability Society Graduate
Scholarship Award in 2008. To date, he has authored / co-authored
around 80 international peer-reviewed publications and an invited book
chapter as well. He is currently a Graduate Student Member of IEEE
(2005-present) and invited member of the IEEE GOLD committee
(2012-2014).
85
International Journal of Materials Science and Engineering Vol. 2, No. 2 December 2014
Kin Leong Pey received his Ph.D. (1994) in
Electrical Engineering from the National
University of Singapore (NUS). He is
currently the Associate Provost (Education) at
the Singapore University of Technology and
Design (SUTD), Singapore and also holds a
concurrent Fellowship appointment in the
Singapore-MIT Alliance (SMA).
He has held various research positions in the
Institute of Microelectronics, Chartered
Semiconductor
Manufacturing
(Global
©2014 Engineering and Technology Publishing
Foundries®) and Agilent Technologies. In the past, he has served as a
faculty member at the National University of Singapore and Nanyang
Technological University (NTU) as the Head of Division for
Microelectronics and Program Director of the Silicon Technology
Research Group. His research interests include dielectric breakdown
and interconnect reliability and failure analysis as well as design for
reliability in integrated circuit and systems. He has published more than
170 international refereed publications and 175 technical papers at
international meetings / conferences and holds 37 US patents.
Prof. Pey is a senior member of IEEE and an IEEE EDS Distinguished
Lecturer.
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