Release 14.7 - xst P.20131013 (nt) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.13 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.13 secs --> Reading design: Pc104_Decoder.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "Pc104_Decoder.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name Output Format Target Device : "Pc104_Decoder" : NGC : XC9500XL CPLDs ---- Source Options Top Module Name Automatic FSM Extraction FSM Encoding Algorithm Safe Implementation Mux Extraction Resource Sharing : Pc104_Decoder : YES : Auto : No : Yes : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal Optimization Effort Keep Hierarchy Netlist Hierarchy : Speed :1 : Yes : As_Optimized RTL Output Hierarchy Separator Bus Delimiter Case Specifier Verilog 2001 : Yes :_ : <> : Maintain : YES ---- Other Options Clock Enable wysiwyg : YES : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "Pc104_Decoder.vf" in library work Module <D3_8E_MXILINX_pc104_decoder> compiled Module <COMP4_MXILINX_pc104_decoder> compiled Module <pc104_decoder> compiled No errors in compilation Analysis of file <"Pc104_Decoder.prj"> succeeded. ========================================================================= * Design Hierarchy Analysis * ========================================================================= ERROR:HDLCompilers:87 - Could not find module/primitive 'Pc104_Decoder' --> Total memory usage is 138868 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)