{I /2224 /2220

.
United States Patent [191
[111
4,044,334
Bachman et a].
.[45]
Aug. 23, 1977
[54]
DATABASE INSTRUCTION UNLOAD
‘
[75]
Invent0r8=
3,821,708
3,878,513
Charles W- B?chman, Lexington;
3,889,243
6/1975
Primak . . . . . . . . , .
3,891,974
3,900,834
6/1975
8/1975
Coulter et a1.
Casey et a1.
3,909,798
9/1975
_
. 1 . .. 340/1725
340/1725
340/1725
Wallach et a1.
340/1725
Honeywell Informatwn 51781991811994
3,916,385 10/1975
Parmar et a1
340/1725
Waltham, Mass.
3,916,387
10/1975
Woodrum
3,938,096
2/1976
Brown et a1.
3,950,730
4/1976
Bienvenu et a1.
[21] APPl- N°-' 588,522
[22] Filed‘
Sokoloff .......... .1 ............ .. 340/ 172.5
Werner
340/1725
Bemamin S. Franklin, Cambridge,
both of Mass.
_
[73] Asslgnw
6/1974
4/1975
June 19’ 1975
. . . ..
340/1725
340/1725
Primary Examiner-Gareth D. Shaw
[51]
1111. 01.2 ........................ .. G06F 9/10; GOGF 9/16;
[52]
US. Cl. ................................... .. 364/200; 364/300
G06}: 9,120; G06}: 13/00
[58] Field of Search ............................. .. 444g
Assistant Examiner-Jan E~ Rhoads
Attorney, Agent, or Firm—Nicholas Prasinos; Ronald T.
Rellmg
[57]
'
[56]
340/ 172.5
.....
ABSTRACT
One of a series of hardware/?rmware primitives is dis
Refe?lnce? Cited
closed for converting a general purpose digital com
U.S_ PATENT DOCUMENTS
, puter into a database machine. The invention comprises
3,248,318: 12/1970
Bartz; et a1. ................... .. 340/1725
’ 4’ 4
10/1971
K11"
3,656,123
3,693,165
3,781,808
3,786,427
3,787,813
4/1972
9/1972
12/1973
1/1974
1/1974
Carnevale et a1.
Reiley et a1.
Ahearn et a1. ..
Schmidt et a1. .
Cole et a1.
. ..
amer """ "
.
a hardware/?rmware implemented machine instruction
which determines the appropriate register where a dam
340/1725
base pointer is currently stored, retrieves the pointer
340/1725
340/1725
340/1725
340/1725
340/1725
f
th t
. t
d th
t
th
. t . t0 main
mm a reg“ er a“
e“ s ores e P01“ er m
mem°ry~
2201
10 Claims, 76 Drawing Figures
1 1317
#2208
$.F1M.
2207
2206
msraucnon
UNLOAD
———-~ INSTRUCTION
D
-
DETECTOR
I
>-—_!
2Z°2\.
OP
com? ADDRESS
P BR
BUFFER
2204
/22o9
Him?“
1
2203
"0" 511's
{I
SCRATCH
0001-: c002 SYLLABLE “B2
INSTRUCTION
ADDRESS
REGISTER
2312?;
/2224
R’w
[22m
221a
/2220
COMPARATO?‘
NOT
‘m0
ILLEGAL
>- 5
“"
FgR-m;
\zzos
I 50034.
EQUAL
5 ii!’
2222
_
/
ADDRESS
CONTROL
umr
2212
/
MEMORY 4000555
1
M55
RESISTER
L
2213
2214
/
z
E312
IE2
“g3
24g;
MEMORY
ACCESS
EXCEPTION
MEMORY
OPERATION
COMPLETE
2221/
if
msmucnou
2223/ COMPLETE
US. Patent
Aug. 23, 1977
Sheet 2 of 28
4,044,334
FIG. 2
2O‘?
BIT NO. O
3I
GENERAL REGISTER
202-7
TAG R|NG
STN
BITN0.0I234
STE
oFFSET
1a
I5l6
3|
0R
TAG RING
STN
8ITN0.0I234
2o3~1
STE
OFFSET
T89IO
3|
BASE REGISTER, INSTRUCTION COUNTER, AND STACK REGISTER
<—~—— MANTISSA
T/
s
204-7
CHARAGTERISTIC
i
BIT N0‘ 0
|5 I6
23 24
3|
MANTISSA—~-——>an NO. 32
\
205?
39 4o
41 4e
55 56
SCIENTIFIC REGISTER (DOUBLEWORD)
e3
r206
BIT NO. 0
21
BOUNDARY ADDRESS REGISTL R
I
cc
BIT NO.
LRN
0
2
I
I 0M I BM
3
4
uM
s
6
ET
GE
HG
4
5
s
M82 @207
T
STATUS REGTSTER
ME
RS
ASR
AME
0
|
2
3
BIT No.
RHU k208
HARDWARE CONTROL MASK REGISTER
LEGEND FOR RESERVED AREAS OF STORAGE IN REGISTERS
AME =
ACCOUNTING MECHANISM
HG
= HARDWARE GATE
AsR =
AuTo STORAGE
LRN = LAST R|NG NUMBER
S
=
SIGN
STE = SEGMENT TABLE
REcoNF|GuRAT|oN
ENTRY
MBZ = MUST BE ZERO
8M
=
BINARY MASK
STN = SEGMENT TABLE
ME
CC
=
CONDITION CODE
CE
=
CORRECTED ERROR
= MACHINE
ERROR
RING = RING NUMBER
DM
=
DECIMAL MASK
NUMBER
TAG =
DESCRIPTOR
TYPE
RHU = RESERVED FOR
HARDWARE USE
UM
=
UNDERFLOW
MASK
ET
=' ENVIRONMENT TOLERANCE
RS
RETRY SUCCESSFUL
US. Patent
Aug. 23, 1977
NAME:
MEMORY
LOCATION
-32
1B ADDRESS
4,044,334
Sheet 3 of 28
CURRENT STATE ENTRY TIME
CET
READY TIME
RTA
ACCOUNTING
WAITING TIME ACCOUNTING
WTA
RUNNING TIME ACCOUNT
RUA
RESIDUAL TIME OUT
RTO
CAPABILITY
PRIORITY
STATE
DEXT
PMW
STATUS
MBZ
MP
MBZ
PMW
OPTIONAL
PMW
DETSZ
DETA
PMW
STWSZ
STWA
STWSZ
STWA
ASW
ASW
EXW
CONTENTS
SKW
1C (DNTENTS
ICW
T
MBZ
BASE REGISTERS SAVING AREA
(8 WORDS)
80
84
400
GENERAL REGISTERS SAVING AREA
WORDS)
SCIENTIFIC REGISTERS SAVING AREA
(8 WORDS)
OPTIONAL
U.S. Patent
Aug. 23, 1977
/5°‘
Sheet4 of 28
4,044,334
FIG. 5
502
_______.__
SYSTEM BASE /
J-TABLE POINTER
/5o5
503
J TABLE If
J
P
NUMBER
NUMBER
504
+
P-TABLE POINTER
P TABLE
506
+
PCB POINTER
506
P68
7a
STACK SEGMENT
o
UNUSED
T REGISTER
(
PORTION
TOP OF STACK
>10|
702A
702
70'\
I! .67 \l CD
woax AREA
SAVE AREA
M
comumcmous
AREA
US. Patent
Sheet 5 of 28
Aug. 23, 1977
4,044,334
FIG. 6
ABSOLUTE ADDRESS 0 --
RESERVE D FOR HARDWARE
BAR
—_
BAR + 4
—>
J TABLE WORD
G TABLE WORD
BAR+ 8
SYSTEM EXCEPTION CELL #0
SYSTE M EXCEPTION CELL #1
SYSTEM EXCEPTION CELL #2
SYSTEM EXCEPTION CELL #3
600
SYSTEM EXCEPTION CELL #4~
SYST E M EXCE PTION CELL #5
SYSTEM EXCEPTION CELL #6
SYSTEM EXCEPTION CELL #7
SYSTEM EXCEPTION CELL #8
BAR + 44 _
CHANNEL EXCEPTION CELL
INTERNAL PROCESSOR QUEUE WORD
BAR + 52 —->
INITIAL
RETRY
COUNT
NFS
CURRENT
RETRY
COUNT
BAR + 56 ——--~
RUNNING PROCESS WORD
BAR + 60 ———>
ATSZ
ABSOLUTIZATION TABLE
POINTER
BAR+ 64 ——I>
CPU SERIAL NUMBER
BAR + 68 —-I»
MAIN STORAGE UPPER LIMIT
BAR + 72 —-¢-
ISL DEVICE
on 4*
BAR+BO
HARDWARE DEVICE
on #
RSU
wag": DEW“: SUBTYPE
RSU
!rsY‘;=E°EV'°E
I
SUBTYPE
BAR + 84
I
BAR+ 88
RESTART ecu.
RESERVED FOR MULTIPROCESSOR
EXTENSIO
> SYSTEM BASE
U.S. Patent
Aug. 23, 1977
Sheet 6 of 28
4,044,334
11/5“
FIG 8
4/502
SYSTEM BASE
/
J-TABLE POINTER
G-TABLE POINTER
SEGMENT Go
INTERNAL PROCESS
QUEUE WORD (IPQW)
gg
READY QUEUE
RUNNING
PROCESS
,
WORD
G
TABLE
G 0
G 1
(52
son“
8-02
WAITING OUEUES
805
FREE
PROCESS LINKS
as
\
G4
RUNN‘NG
\\
G5
802
6"
802a‘
sesmam- Gn
; PROCESS PCB
//-806
US. Patent
Aug. 23, 1977
4,044,334
Sheet 8 of 28
CAPABILITY
I001
PRIORITY
1002
STATE
I003
DEXT
I004
BYTE
BYTE
BYTE
NUMBER
___-_
’' ACCOUNTING MODE - I005
=
SCIENTIFIC MODE —- IOOG
—'—-————> CODE MODE CAPABILITY - I007
o
o o o
0
FIG
lOb
IOOI
o o o o
FIG
10¢
10B
1012
|0I4
|on
|o|5
I010? _|
BIT POSITION
I- [-1016
A
S
o
l
55
2
STATUS
~
--
MBZ
WIOOES
d
5
MP
MBZ
IOI8
1on9
FIG IOe
I5 I6
SE6
a \4
O
—
W
o
4
IOI?
7 8
I020?
’
3
MBZ
nous
O
MOI EX“) 0
23 24
I02!
7
'
3| BIT NO.
SRA
* .*
FIG IQf
7 e
MEANINGLESS
I022
\5/@
23 24
3l/BIT N0.
EXCEPTION CLASS AND TYPE
IO23
U.S. Patent
Aug. 23, 1977
Sheet 10 of 28
||o|7
H027
JTSZ
an no.
J TABLE POINTER
0
1 a
3|
H037
H047
PTSZ
5mm.
P TABLE POINTER
0
"re
H057
3|
H067
P
BIT NO.
MBZ
0 I
H077
PROCESS CONTROL BLOCK POINTER
7 8
3|
H087
H097
GTSZ
an no.
0
3 TABLE POINTER
"r a
|||2
‘
IIH
3|
m3
|||4
HID-IP
1
|——_[—H\5
“'6 7
A u w as
WORD 0|
an'no.
BASE/I5
0|23456‘7
INT?
WORD .1.
BIT NO.
4,044,334
FIG. 11e
"I87
RSU
32
FIG. 11‘?
3|
U.S. Patent
Aug. 23, 1977
11207
Sheet 11 0128
4,044,334
11217
MBZ
11227
G
D
BIT NO.
°
“F16 i'i
3'
11237
11247
MHZ
HEAD OF Q/PR/RDY
BIT NO.
°
FIG ‘i111
1125-?
N261
11277
Rmwnc'sbm
RE$S$TSI1T~T J
""5
BIT NO.
0
FIG
l5
.
23 24
3|
1130
1131
N287
1129?
NFS
BIT NO.
0
PRI
1a
FF‘IBZ
s
ARN
11337
JP
II|2|3I4|5|6
31
FIG 11 j
11347
11357
ATSZ
BIT NO.
o
“BSOLUTIZATION TABLE POINTER
1 a
a1
H367
CPU SERIAL NUMBER
BIT NO.
FIG. 11 Q
U.S. Patent
Aug. 23, 1977
Sheet 12 of 28
4,044,334
"397
H377 H387
F
BIT NO.
000
MAIN STORAGE UPPER LIMIT
0 I
3|
H407
n4?
ISL DEVICE c~#
BIT NO.
0
I5 l6
H427
H437
RSU
BIT NO.
0
0
I
7 e
I
SUBTYPE
23 24
H497
3|
H50?
0
7 s
3|
H47?
IsI_ DEVICE
TYPE
M52
SUBTYPE
23 24
H467
H487
H447
HARDWARE DEVICE
TYPE
RS“
BIT N0.
3\
7 a
H45‘?
BIT NO.
HARDWARE DEVICE c~#
D
l5 I6
31
RESERVED FOR MULTIPROCESSOR EXTENSION
BIT N0.
3|
FIG. 11 r
U.S. Patent
Aug. 23, 1977
‘307
\—'
Sheet 14 of 28
4,044,334
CENTRAL PROCESSING UNIT (CPU) I04
GENERAI. REGIsTERs
I308
\-,
I309
BASE REGIsTERs
SCIENTIFIC REGIsTERs
--/
'3‘°\~
T- REGISTER
sTATus REGISTER
J13"
'3'2\~
INsTRucTIoN couNTER (1c)
HARDWARE coNT. MASK REG.
»-\
,
l3|3
SCRATCH
PAD
c
MEMORY
I3I5o
(LSU)
_
INDEX
REGISTERS
E
INsTRuGTIoN
FETCH UNIT
/EMULATION
BIG
o
0
o
D
-
CLOCK
CONTROL
0
n
O
n
UNIT
DATA
(Aw)
MANAGE
TIMING \
SIGNALS ‘-
l3l9
(IFU)
UNIT
o
UMT
/
::
MENT
UNIT
To ALL ’
(DMU)
FRACTIONAL
UN‘TS
‘m
(EIA)
132i
‘320
" ARITH.
/ LOGIC
I317
uNIT
Assoc,
.
"AUX,
Q
i
I
Q
.
I
O
O
O
l3l9cI
/ MEI/I
l3|7u
I
MIcRD DPERATIDN
BRANCH DDNDITIDN
, SIGNALS FROM
/ SIGNALS To
I322
FUNCTIONAL
UNITS
UNITS
I302‘)
fl30l
f?reTéqFg'aEsToRE
'
CONTROL STORE
ADAPTER
UN'T
(cm
(05“)
I305)
(I304
INPUT/OUTPUT
CONTROL uNIT
I
‘323
FUNCTIONAL
CONTROL AND
:) LOAD UNIT
(Ioc)
[I303
CONTROL sToRE
LOADER
(CLU)
(csLI
_ MIC R0 INSTBUCT IONS
'F/G. l3a
'
EQ/
'
US. Patent
Aug. 23, 1977
4,044,334
Sheet 15 0f 28
TESTS
[I334
549"}
sELEcT DR
FOURTH
SELEcT a MASK
csu SEQUENCE coNTRoL
LEVELW)
(MICROPROGRAM)
csu SEQUENCE coNTRoL
RETURN
L
BRANCH
(HARDWARE)
L
HARDWARE
ADDRESS
BRANCHES
GENERATED
,MT‘AUZH
O
SOFT CLEAR
0
coNTRoL sToRE LOAD
o
coNTRoL sToRE SCAN
ENTER MAINT PANEL
ADD
REG'STEFLB
0
6 7
'0
"
_
'2
'3
t
C TEST D TEST
5'0
KSO-G
‘3
RESULT RESULT
'-
kg‘T’?‘égw
L
REG'STER
BTEST CTEST DTEST
E"
BRANCH
KS0-6 RESULT RESULT RESULT
0
13,47
MP SWITCHES
SECENPT)
ENTER MAINT CHANNEL 0M8 (Is _ an
SOFTWR ERRDR
_|
_
5-3
E=4
HARDWR EXIT
HARDwR ERROR
‘336
[:5
KR REG|STER
E=6,7 KS INCREMENTOR
2
4
(35,0005
8
KA REGISTER
N M
c3
(:4
L
v LK
RETURN
BRANCH
L
REGISTER
ADDRESS (KNA)
RETURN
I
‘335
BRANCH
|NTERR
RETURNUPT
(KA)
REGISTER
(KR)
\I339
j 1
i
155%55
u
R
323‘???
(KS)
HISTORY (KH) /'340
+1
INCREMENTOR
__J
REGISTER
‘337
F
_.__ . __L__L_
I338]
(Is-3n )
i
'
7
/—|333
1
coNTRoL
4
sToRE
I
MICRO-OPERATION
3
SIGNALS To CPU
|
,_
i
ARRAY
‘i
I360 l36l
lI
1
READ LATcHES I357
1
}
0
__
__
a
0
n
o
tS
's
's
's
'5
’s
___!
ID
*b
,c
B
y
rd.-
.
Pq
v-r
i
MICRO-0P
‘
1r
DECODER
:
g
5
L
K
COMPARE
w
‘359
Y8 Y0 Y0 YL
I353
K552 1
E
0-0
I343
‘344
MAINTENA c
['35'
CSSMQEE
05:20:05
ADDRESS
oouNT
J
sYNc.
SYNC.
\
“mar E BUS
MULTIPLEXOR
T
T (KQM)
T T
KNA KH
KA
KR
/|345
T
T
KS
KP
9
);
v
REGISTER
1
I365
_
PANEL
Ks
[364
l
To CPU
‘350
I363
n
.355\- MAINT.
OM51
use
l
NEXT I342
|34l
ADDRESSINFO. NExT COMMANDS
|___’__j___
L
_]
OMB
___LL,__4___.~__¢_SU_
I30l"~|
‘
1
THIRD
'
US. Patent
Aug. 23, 1977
4,044,334
Sheet 16 of 28
NO
IT
6:
YES
I482
‘
l5
F'RN ZARN
YES (\l483
SET AB
AND ARN
IN BAR+56
ASYNCHRONOUS
TRAP
I486
IS
RUN
EMULATION
MODE
DEXT=O_?
YES
FIG‘. /4/'
RUN NORMAL
MODE
/
MAIN
FlELD
USES
FIELD
NAME
I326
SEQUENCE
TYPE
E
f
I327
f
f
BRANCHING
AND / OR
AND
MICRO-OPS DESIGNA-HON
A B C D L
K
6 4 6 6 1
BITS
I328
I329
DATA
TO
BUS
QA
QB
4
4
f
I330
MICRO-OPS CHECKING
F
p
32
4
3
23
l4
8
FIG. I30
~‘325
US. Patent
Aug. 23, 1977
D's
Sheet 17 of 28
4,044,334
I40!
FETCH IPQW
FROM sYsT BASE /
.402
TO SCRATCH
PAD
I404
EGO-FETCH
GO SEQ. DESC.
IS
THERE
A PROCE SS
CUR RENTLY
RUNNING
FETCH HEAD OF
READY QUEUE
(GO, IPQW)
/ l4 l2
RUN HEAD
OF READY
QUEUE
|4I3
FETCH PRIORITY
BYTE OF CURRENT
PROCESS (CJP) FROM
/
PROCESS MAIN WORD
O PMW O
LOWER PRIORITY
THAN PROCESS AT
HEAD OF READY
TS
CJP RUN~
NING IN DECO?
RESET CONTEST
QUEUE NJP?
INDICATOR
EXTENSION
MODE
mm
(N0)
(YES)
l4l9cI
NEXT INST
EMULATION MODE
FIRMWARE
| RITY
B
PRO
8U
‘4'8
(FIRMVT‘RE
RLLO’ ‘4'9
SUBRO'ITINE
(9
‘4'9!’
6.
NEXT INST
NATIVE MODE
a
US. Patent
Aug. 23, 1977
Sheet 18 of 28
g) [I420
UPDATE DEXT
NO IN PMWO
V
[I422
FETCH
BAR
"
f I423
FETCH RUNNING
PROCESS WORD
(RPW) AT
BAR + 56
V
[I424
FETCH
PMW 0
PLACE PROCESS
LINMPL) IN RPW
(WRITE NJP
[I433
IN RPW)
V
[I425
TEST.‘
MBZ FIELD
OF PMWO
DEQUEUE PL
FROM
0/ PR /RDY
$0
I434
l425cI
FIRMWARE
SUBROUTINE
UQLK
[#426
PLACE OLD
RPW, .JP NO. IN
A PROCESS
FETCH
PMW 1
[I435
TEST;
MBZ FIELD
OF PMWI
#0
LINK IN
Q/PR/RDY
PROCESSOR
TO VACANT
F/G. /4b
FIG‘. /4a
U.S. Patent
Aug. 23, 1977
Sheet 19 0f28
(‘I436
FETCH
ASW O
‘
4,044,334
(#442
FETCH
STOCK WORD
SKW
[#437
TEsT:
3M6;
W
MUST BE =7
‘@
>7
s T
f
@
OF SW
#20
=0
I438
I443
f I444
FETCH
FAIESLC‘H
INSTRUCTION
COUNTERWORD
I cw
TEST:
TEST
OF ASWI
MUST BE ss
‘
>8
0
F
#0
ICW
s8
:O
p.440
FETCH
EXCEPT ION
WORD Exw
(#446
FETCH
M 82
WORD
I44!
1
F
I44?
TEST
TEST
MBZ ETELD
M82 HELD
OF EXW
$0
:0
(BITS 0-31) OF
MBZ WORD
‘
=0
#0
I448
FETCH
STACK BASE
WORDS 0,1 , 2
(saw 0,1,2)
F/G. /4d
F/G. I46’

Download Report