The Impact of Scaling on the Design of High - ETH E

DISS. ETH NO. 23402
The Impact of Scaling on the
Design of High-Speed
Delta-Sigma A/D Converters
A thesis submitted to attain the degree of
DOCTOR OF SCIENCES of ETH ZURICH
(Dr. sc. ETH Zurich)
presented by
LUCA BETTINI
MSc Electronic Engineering, Politecnico di Milano
born on September 12th, 1982
citizen of Italy
accepted on the recommendation of
Prof. Dr. Qiuting Huang, examiner
Prof. Dr. Yiannos Manoli, co-examiner
2016
Abstract
The evolution of the semiconductor industry during the last 50 years
has been propelled by the tremendous progress achieved by the Complementary Metal-Oxide-Semiconductor (CMOS) manufacturing process.
Digital integrated circuits (ICs) have widely profited from CMOS scaling
in terms of area, power, and speed, becoming the driver for the adoption
of more and more advanced technology nodes. On the other hand,
analog/mixed-signal ICs, challenged rather than favored by scaling, have
struggled to keep the same progress pace. Therefore, the question
arises whether it makes sense or not to scale analog-dominated integrated circuits into deca-nanometer CMOS processes. This dissertation
investigates technology opportunities and design challenges offered by
advanced sub-100 nm CMOS processes, with a particular emphasis on
the impact of scaling on the design of high-speed delta-sigma analogto-digital converters (ADCs). The main shortcomings resulting from
scaling are discussed, and circuit techniques aiming at combating such
drawbacks are presented. In order to vindicate the theoretical findings
and draw conclusions on the effect of scaling, the very same third-order
discrete-time (DT) delta-sigma modulator topology has been implemented first in a mature 130 nm bulk CMOS process, and later in an advanced 28 nm FD-SOI CMOS technology. The former implementation
achieves 63 dB dynamic range (DR) in a 25 MHz bandwidth (BW). The
latter design features 64 dB DR in a 50 MHz BW while occupying half
the area and consuming down to half the power when operated at the
same speed. The two ADC prototypes were conceived as the basis for
the development of new product lines for 4G wireless communications
supporting up to full intraband carrier aggregation.
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Sommario
Lo sviluppo dell’industria dei semiconduttori negli ultimi 50 anni è stato
reso possibile dagli enormi progressi raggiunti nei processi di fabbricazione Complementary Metal-Oxide-Semiconductor (CMOS). I circuiti
digitali integrati hanno ampiamente beneficiato dallo scaling in termini
di area, potenza e velocità, giustificando l’adozione di tecnologie sempre
più avanzate. Al contrario, i circuiti integrati analogici e mixed-signal,
ostacolati piuttosto che favoriti dallo scaling, hanno da sempre faticato a
mantenere lo stesso tasso di progresso. È quindi ragionevole domandarsi
se abbia senso o meno realizzare circuiti prevalentemente analogici in
tecnologie CMOS deca-nanometriche. Questo lavoro di tesi descrive
le opportunità e le sfide legate alla progettazione di circuiti integrati
in processi CMOS sotto i 100 nm, con particolare attenzione all’impatto della miniaturizzazione sulla realizzazione di convertitori analogicodigitali delta-sigma ad alta velocità. Le principali problematiche derivanti
dallo scaling sono discusse, e tecniche circuitali volte a contrastare tali
limitazioni sono presentate. Per dimostrare l’efficacia delle soluzioni
proposte e trarre conclusioni sugli effetti dello scaling, la medesima
topologia di convertitore ∆Σ a tempo discreto del terzo ordine è stata
realizzata prima in tecnologia CMOS 130 nm e, successivamente, in un
processo FD-SOI CMOS da 28 nm. La prima implementazione circuitale
copre una banda di 25 MHz con un range dinamico (DR) di 63 dB,
mentre la seconda supporta una banda di 50 MHz con un DR di 64 dB,
dimezzando l’occupazione di area e con un consumo di potenza fino al
50% inferiore a pari velocità. I due prototipi sono stati concepiti come la
base per lo sviluppo di nuove linee di prodotto per comunicazioni cellulari
di quarta generazione.
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Zusammenfassung
Die Evolution der Halbleiterindustrie wurde in den letzen 50 Jahren
von den ungemeinen Fortschritten im Complementary Metal-Oxide-Semiconductor (CMOS) Herstellungsprozess vorangetrieben. Digitale integrierte Schaltungen haben einerseits von der CMOS Skalierung in
Hinsicht auf Größe, Leistung und Geschwindigkeit stark profitiert und
haben dadurch die Verwendung neuer CMOS Technologien intensiviert.
Andererseits werden analoge und mixed-signal integrierte Schaltungen
durch die Skalierung eher vor größere Probleme gestellt, als daß ihre Entwicklung erleichtert wird. Dadurch ergibt sich die Frage, ob es überhaupt
sinnvoll ist, analog-dominierte Schaltungen in deca-nanometer Prozeßen zu entwickeln. Diese Dissertation untersucht die Vor- und Nachteile von fortgeschrittenen CMOS Prozeßen unter 100 nm, und konzentriert sich besonders auf die Wirkung der Skalierung auf die Entwicklung
von high-speed delta-sigma Analog-Digital-Wandlern. Die Hauptprobleme, die durch die Skalierung entstehen, werden in dieser Arbeit diskutiert, und entsprechende Lösungen und Schaltungstechniken werden
präsentiert. Um die theoretischen Resultate zu untermauern und um
Schlüße uber die Skalierung ziehen zu können, wird der gleiche discretetime (DT) ∆Σ Modulator dritter Ordnung sowohl in einer reifen 130 nm
bulk CMOS Technologie als auch in einem 28 nm FD-SOI Prozeß implementiert. Die erste Realizierung erreicht 63 dB dynamic Range (DR)
und 25 MHz Bandbreite, während die zweite Realizierung 64 dB DR
und 50 MHz Bandbreite bei halbem Platzbedarf und je nach Modus
nur halber Leistungsaufnahme erreicht. Die zwei Prototypen werden
vorgestellt, um als Grundlage für die Entwicklung von neuen Produkten
für 4G wireless Anwendungen zu dienen.
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