FM4 ファミリ
32 ビット・マイクロコントローラ
FM4
ペリフェラルマニュアル タイマ編
Errata Sheet
ページ
場所
訂正内容
Original document code: MN709-00002-3v0-J
Rev. 1.0 February 25, 2015
743
750
Appendixes
A.レジスタ
マップ
Appendixes
A. レジスタ
マップ
以下の
に示すように訂正。
(誤)1.44.1
TYPE1-M4, TYPE2-M4, TYPE3-M4 products
(正) 1.44.1 TYPE3-M4 product
P750 の次ページから添付資料 1 を追加。
Publication Number FM4_MN709-00002-3v0-J-DE
CONFIDENTIAL
Revision 1.0
Issue Date February 25, 2015
E R R A T A
S H E E T
<添付資料 1>
1.47 GDC Sub system controller
GDC Sub system controller
Base_Address : 0xD0A0_0000
Register
Base_Address
+ Address
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
+1
LockUnlock[W]
LockStatus[W]
-------- -------- -------0 ---0---0
*[W]
CnfigClockControl[W]
-------- -------- -------- -----001
VRamInterruptEnable[W]
-------- -------- -------- ------11
*[W]
VRamInterruptClear[W]
-------- -------- -------- ------00
VRamInterruptStatus[W]
-------- -------- -------- ------00
ExtFlashDevSelect[W]
-------- -------- -------- -------1
VRamRemapDisable[W]
-------- -------- -------- -------0
PanicSwitch[W]
-------- -------- -------- -------1
GDC_ClockDivider[W]
-------- -----100 00000000 -------WkupTriggerMask[W]
-----000 -----000 00000000 00000000
ClockDomainStatus[W]
-------- -------- -------- ----0000
0x03C
-
0x048
0x04C
0x050
+0
00000000 00000000 00000000 00000000
-
0x044
CONFIDENTIAL
+2
0x038
0x040
2
+3
dsp_LoxkUnlock[W]
00000000 00000000 00000000 00000000
dsp_LockStatus[W]
-------- -------- -------0 ---0---0
dsp0_ClockDivider[W]
-------- 01000001 11100000 -------dsp0_DomainControl[W]
-------- -------1 -------- -------0
dsp0_ClockShift[W]
-------- -------- -------- -------1
FM4_MN709-00002-3v0-J-DE1, February 25, 2015
E R R A T A
S H E E T
Register
Base_Address
+ Address
0x054
0x058
0x05C
0x060
+2
+1
dsp0_PowerEnControl[W]
-------- -------- -------- -------0
dsp0_ClockGateModeLock[W]
00000000 00000000 00000000 00000000
dsp0_ClockGateControl[W]
-------- -------- -------- -------0
-
0x068
-
0x06C
-
0x070
-
0x074
-
0x07C
0x080
0x084
0x088
0x08C
SDRAMC_ClcokDivider[W]
-------- 00000100 00000000 -------SDRAMC_DomainControl[W]
-------- -------1 -------- -------0
HSSPIC_ClockDivider[W]
-------- 00000100 00000000 -------HSSPIC_DomainControl[W]
-------- -------1 -------- -------0
RPCC_ClcokDivider[W]
-------- -------- -------- -----000
RPCC_DomainControl[W]
-------- -------1 -------- -------0
0x090
-
0x094
-
0x098
-
0x09C
-
0x100
0x104
0x108
0x10C
February 25, 2015, FM4_MN709-00002-3v0-J-DE1
+0
*[W]
0x064
0x078
CONFIDENTIAL
+3
vram_LockUnlock[W]
00000000 00000000 00000000 00000000
vram_LockStatus[W]
-------- -------- -------0 ---0---0
vram_sram_select[W]
-------- -------- ----0000 00000000
*[W]
3
E R R A T A
S H E E T
Register
Base_Address
+ Address
+1
*[W]
0x114
*[W]
0x118
*[W]
0x11C
*[W]
0x120
*[W]
0x124
*[W]
0x128
*[W]
0x12C
-
0x130
-
0x134
-
0x138
-
0x140
0x144
0x148
0x14C-0xFFC
CONFIDENTIAL
+2
0x110
0x13C
4
+3
+0
vram_sberraddr_s0[W]
00000000 00000000 0000000 00000000
vram_sberraddr_s1[W]
00000000 00000000 0000000 00000000
vram_arbiter_priority[W]
-------- -------- -------- 00000000
-
FM4_MN709-00002-3v0-J-DE1, February 25, 2015
E R R A T A
S H E E T
1.48 GDC Sub system SDRAM controller
GDC Sub system SDRAM controller Base_Address : 0xD0A3_0000
Register
Base_Address
+ Address
0x000-0x0FF
0x100
0x104
0x108
0x10C
0x110
0x114-0xFFC
February 25, 2015, FM4_MN709-00002-3v0-J-DE1
CONFIDENTIAL
+3
+2
+1
+0
SDMODE[W]
-------- -------0 00010011 --00-000
REFTIM[W]
-------0 00000000 0000000000110011
PWRDWN[W]
-------- -------- 00000000 00000000
SDTIM[W]
0-----00 01000010 00010001 0100--01
SDCMD[W]
0------- ---00000 00000000 00000000
-
5

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