高集積化フロントエンドのトレンド
~CMOSピクセル・放射線耐性~
University of Bonn
岸下 徹一
[email protected]
20-21 Nov. 2014, 計測システム研究会@J-PARC
Outline
✓ Introduction (自己紹介)
✓ ハイブリッドピクセル検出器 (HEP Tracker)
• Pixels@LHC
✓ (セミ) モノリシックピクセル検出器
• DEPFET
• Depleted MAPS
✓ テクノロジーのトレンド
• Smaller feature-size (TSMC 65 nm CMOS)
etc…
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
2
Bonn大学における研究状況
Bonn大学における研究状況
2010.06~
./012"#,3$
2014.06
(現在)
H,G0!,&4$,60
Group Prof. Norbert Wermes
高エネルギー実験用のfront-end ASIC及び
N>=OMP>05Q?>R=0JLD0&"0
=%B/0E-@0!0J-A0""F0
S#4/0#&.0?6/#$0'%7&#60
:#'405Q0$#";0T,$0?6/#$0
H#.-05#$.0;$,I/.02E@0>$#.90
ピクセル検出器の開発で中心的な役割
ATLAS
,&'
.5!678'
B@'=D5=E5>?'
E(%/'"%./"('9%7()"
A9"45">>F"
26"1=0!"
ASIC
design
RW"
- FE-I3, FE-I4 chip design
- Hybrid pixel detector, bump
- IBL module production
- Diamond detector
- 3D sensor, TSV technology
Belle II
- DHP chip design
- PXD module testing
- DEPFET sensor testing
!"#$%&#'()&%*+,&&-./0
Borrowed from home page
Our group is developing full custom chips since 1994. Up to now, more
than 40 designs have been submitted and successfully tested. They vary
from simple transistor test structures to full readout chips for silicon strip
and pixel detectors. At the moment, we are working on 8 workstations with
the CADENCE software using different CMOS technologies. Further down
this page lists the designs starting with the most recent submissions.
アナログfront-endデザインを中心となって進めている
T. Kishishita
%-'$
'4%$
!"
20-21 Nov. 2014, 計測システム研究会@J-PARC
2
3
ハイブリッドピクセル検出器
+
+
-
T. Kishishita
good S/N←fully depleted
fast R/O→~ns time stamp
radiation length→ 3.5% x/X0
spatial resolution→~10 μm
bump bonding
20-21 Nov. 2014, 計測システム研究会@J-PARC
4
LHCにおけるピクセル検出器の現状
ハイブリッドピクセル検出器
(state
of the art)
Hybrid Pixel
Detectors
for the LHC
sensorとASICは別プロセス
first use in 1992, OmegaD (103 pixels)
ATLAS
Hybrid Pixel Detector (state of the art)
シリコンピクセル検出器
~1.8 m2, 50x400 um2 cells, 80x106 pixels
フリップチップ
CMS
バンプボンディング
フロントエンドASIC
• amplification by a
dedicated R/O chip
• 1-1 cell correspondence
ALICE
~0.2 m2, 50x450 um2 cells, 10x106 pixels
~1m2, 100x150um2 cells, 33x106 pixels
全実験でInnermost layerにハイブリッドピクセルを使用
T. Kishishita
SSI, 07/20/2006
20-21 Nov. 2014, 計測システム研究会@J-PARC
5
ATLASシリコンピクセル検出器
Siセンサー
✓50 × 400 um2, 250 um thickness
✓n+ pixel on n- material
✓rad-hard (1015neq, 80 Mrad)
✓p- after irrad. (can be operated
partially depleted)
ハイブリッドプロセス
✓PbSn or In bumping (wafer scale)
✓IC wafers thinned after bumping
~180
um
Hybridto
Pixels
/ HEP
/ technical issues / hybridization
bumping & flip chip of thinned bumped (!) chips (~ 180µ m, 8“ wafers) ➼
ATLAS / CMS / ALICE
Indium
50 µ m
photo AMS, Rome
T. Kishishita
20-21
• „lift off“ + thermo compression
• bumps „soft“ + „thin“ (~6 µ m)
Nov. 2014, 計測システム研究会@J-PARC
- module handling more „touchy“
ATLAS / ALICE
Solder (PbSn)
50 µ m
photo IZM, Berlin
• electroplating + reflow
• automated wafer scale process @ v
• bumps strong and „larger“ (~25 µ m
7
ハイブリッドピクセルの読み出し原理
センサーで電荷生成→フロントエンドASICで信号処理
indiv. cell R/O
各BX time間のヒット信号を保持 (dig./ana.)
トリガー同期のヒットピクセル読み出し
RAM
pixel cell
✓PNダイオード→Qsignal
✓センサーに最適化したFront-end ASICで信号増幅+波形整形
(ピクセル電極と読み出し回路をバンプボンディングで接続)
✓各ピクセルのヒット情報を保持(アドレス、電荷、時間情報)
✓End of Columnロジック(トリガー待機)
✓カラム読み出し
transfer
on chip
Store
end of column
storage & logic
• アドレス
• 電荷 (ToT)
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
• 時間情報
6
ATLASフロントエンドASIC: FE-I3
複数のプロセスで試作(DMILL, BiCMOS)
✓0.25 μm CMOSプロセス
✓80 Mrad, 1015 neq/cm2
Pixel cell
✓ピクセルサイズ: 50×400
11
mm
μm2
✓18 column × 160 rows = 2880 cells
✓各ピクセルにCSA, zero-suppression
✓低消費電力: ~50 μW/pix
✓低雑音: ~250 e✓閾値のばらつき: ~70e- (after tuning)
7.4 mm
End of columnロジック
✓40 MHz clockでタイムスタンプ
✓データバッファリング(2.5 μs trigger latency)
✓ヒットセレクション
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
8
• 
Planar Slim Edge Sensors (CiS)
• 
oxygenated n-in-n
silicon; 200 µm thick
IBL(Insertable
B-Layer)
• 
minimize inactive edge by shifting
• 
3D Slim Edge Sensors (FBK and CNM)
• 
partial 3D: electrodes etched from both side
• 
p-type substrate; 230 µm thick
• 
no active edge
V
~10V, spatial resolution as for
layer)! C.depl.
Gemme will discuss this tomorrow
sLHC data rates
layout pixels
guard-ringIBL
underneath
Innermost layerに4層目を追加(nearest BX
sensor technologies:
Hit inefficiency rises
withμm)
planarsteeply
pixels (~12
e chip (DC) modules with 2 FE-I4 and 1 planar n-in-n
sensor
tile
the
hit
rate
2種類のセンサーを採用
chip
(SC) modules with 1 FE-I4 and 1 n-in-p 3D sensor tile
Planar sensor (n-in-n)
3D sensors (n-in-p)
Bottleneck: congestion in double
200
230
m thickness
inactive edge <250
(minimize gaps in
m
, no overlap)
low Q generated after irradiation
! low threshold operation and high HV
cheaper and easier to fabricate
m thickness
inactive edge 200
1-
column readout
m
50 μm
more local in-pixel storage
(130 nm !)
low depletion voltage (<180V)
>99% of hits are not triggered
even after high doses
electrode orientation suitable don’t move them
for
highly inclined tracks
75% planar 25% 3D sensors (large
(drawing
outdate:
columnsCNM(Barcelona)
penetrate full s
Stanford,
SINTEF(Oslo),
IRST(Trieste),
)
フロントエンドASICも改良(FE-I4)
✓250 nm→130 nm CMOS
✓ピクセルサイズ: 50×400 μm2
→50×250 μm2
Fabian Hügging
✓データレート:40 Mb/s→160 Mb/s
Fabian Hügging – University of Bonn – September - 17 - 2013
✓ローカルバッファを採用
– University of Bonn – September - 17 - 2013
7
6
✓(Serial powering)
T. Kishishita
PSD8計測システム研究会@J-PARC
Glasgow, 9/5/2008 – N. Wermes, Bonn
20-21 Nov. 2014,
9
フロントエンドアーキテクチャ(ATLAS)
Functions inCMSはアナログ”アーキテクチャ
the cell (binary readout + „poor man‘s“ analog)
“ATLASはデジタル,
ToT
Feedback
tr
tf
Bump bond contact
Hit
Calibration
charge
injection
Strobe
Select
Calibration voltage
Address
ROM
(6+1)-bit
local threshold
DAC
Global time stamp
(40 MHz gray counter)
Global
threshold
- Integration of signal charge by charge sensitive amplifier
- Pulse shaping by feedback circuit with constant current feed back
✓Integration
of signal charge by charge sensitive
- Hit detection by comparator
✓Pulse
shaping with constant current feedback
- ~5 bit analog information via „time over threshold“
✓Hit
detection
byandcomparator
- storage
of address
time stamps in RAM at the periphery
Falling
edge
RAM
Leading
edge Priority
logic
RAM
Hit data &
Arbitration logic
Bus to column controller
amplifier
✓~5 bit analog info. via “time over threshold” (small
time etwalk
with
small
Q)
L. Blanquart
al., NIM-A
456 (2001)
217-231
✓storage
SSI, 07/20/2006 of address and time stamps in RAM at the periphery
T. Kishishita
N. Wermes
20-21 Nov. 2014, 計測システム研究会@J-PARC
52
10
mechanism, comparator
threshold:
analog readout of PSI46
フロントエンドアーキテクチャ(CMS)
8 bits global
4 bits local trim
40 MHz, 20 MHz fallback
pixel address:
アナログブロック
3 cycles header per chip
9 bits digital
header
dc
pixel
aout
251 transistors per pixel
addresses analog coded
g
Pixel
6 levels
address
X1
2 cycles double columnA
se,
0-1V
9
D
global
3threshold
cycles pixel row
Trim
4 bit
Mask
bit
1 cycle analog pulse height
address
Double column bus
repeated
✓0.25 μm
CMOS for each hit
✓pixel size: 100 × 150 μm2
readout
pass returns
data
✓CSA,each
Shaper,
Sample/hold,
comparator
✓251 fets
pixone trigger number
for per
only
✓52 × 80 = 4160 pixels
pulse height
1 pixel hit
✓5 clock cycleで11ビットのアドレス情報を
エンコード(6 levels)
✓1 clock cycleでアナログ波高値
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
11
放射線によるピクセル検出器への影響
Total
ionizing dose (TID) effects
FEへの影響
X-ray irradiation at CERN
センサーへの影響
✓ゲート酸化膜への電荷蓄積
1) Positive chargesバルクダメージ(NIEL)
in the gate oxide
.........
✓change
3) STI
effect of doping concentration
RD50 approaches to de
RD50
(Shallow
Trench inversion”
Isolation)
→”type
+++
radiation
harder
tracking
onics … and cure
Top view of MOSFET
✓leakage
current
→noise,
power
• Material
Engineering
-Defect
Engineering
of Silicon
+++
+++
iO and
• Understanding radiation damage
✓チャージトラップ
→signal
2
Feld-Oxid
GateOxid
Gate
Drain
Source
n+
n+
✓界面トラップ (Si-SiO2)
sizes
µm)
2)(≤ 0,35
Interface
traps (Si02- Si)
nnel out
✓STI
トランジスタのVth shift (good in DSM,
p-Substrat
Leckstrom
e-electrodes +
• Macroscopic effects and Microscopic defects
• Simulation of defect properties & kinetics
サーフィスダメージ(IEL)
• Irradiation with different particles & energies
• Oxygen
rich Silicon
D
S
G
• DOFZ, Cz, MCZ,
EPI
✓界面トラップ,
SiO2への電荷蓄積
• Oxygen dimer & hydrogen enriched Silicon
→breakdown
behavior
• Influence
of processing
technology
Either
the nm
STI oxide
and STIgate
interface
but larger
leak),traps influence the
dox<10
• Material Engineering-New Materials (work concluded)
(SiC), Gallium Nitride (GaN)
field
of the current→ELT
gate, and therefore the electrical parameters. •+++Silicon Carbide +++
leakage
SEU (ビット反転)→DICE SRAM
T. Kishishita
CPIX14, 15-17 Sep. 2014, Bonn
Gate
Drain
T. Kishishita
Source
diamond
• Device Engineering
(New Detector Designs)
W
• p-type silicon detectors
17/21 (n-in-p)
• thin detectors
• 3D detectors
• Simulation of highly irradiated detectors
• Semi 3D detectors and Stripixels
• Cost effective detectors
20-21 Nov. 2014, 計測システム研究会@J-PARC
Related
•“Cryo
• “Diam
• Mono
• Detec
12
Pixels@HL-LHC
Pixels at sLHC: radiation tolerance
trend:
n+ on n→n+ on p (FZ or MCZ)
signal [electrons]
25000
FZ Silicon Strip Sensors
p-Fz (500V)
p-Fz (800V)
20000
Data from Gianluigi Casse et al. (Liverpool)
presented on VERTEX 2008
3D simulation
Pennicard 2007
15000
@1016
n-FZ (500V)
10000
7500
diamond
5000
6000
2500
14
10
15
5 10
-2
[cm
]
eq
16
5 10
M.Moll - 08/2008
n-in-p (FZ), 300
n-in-p (FZ), 300
n-in-p (FZ), 300
n-in-p (FZ), 300
n-in-p (FZ), 300
n-in-p (FZ), 300
p-in-n (FZ), 300
p-in-n (FZ), 300
m, 500V, 23GeV p
m, 500V, neutrons
m, 500V, 26MeV p
m, 800V, 23GeV p
m, 800V, neutrons
m, 800V, 26MeV p
m, 500V, 23GeV p
m, 500V, neutrons
Double-sided 3D, 250 m, simulation! [1]
Diamond (pCVD), 500 m [2] (RD42 data!)
3D Si simulation
p – FZ planar Si
N.Wermes
diamond
ATLAS DBM
[1] 3D, double sided, 250 m columns, 300 m substrate [Pennicard 2007]
o
[2]
[3] Diamond
p/n-FZ, 300
[RD42
m, (-30
Collaboration]
C, 25ns), strip [Casse 2008]
note: neq (Si) normalization (correct for diamond?) & diamond better in S/N terms
T. Kishishita
20-21
1317
PSD8 Glasgow, 9/5/2008 – N. Wermes,
Bonn Nov. 2014, 計測システム研究会@J-PARC
(セミ) モノリシックピクセル検出器
+
+
+
+
-
T. Kishishita
no bump bonding
very thin (50-75 μm)→~0.2% x/X0
small pixel size (20-50 μm)→~1μm resolution
low power→less cooling
radiation hardness
R/O speed
20-21 Nov. 2014, 計測システム研究会@J-PARC
14
モノリシックピクセルの読み出し原理
select line
電荷生成と信号処理に共通のSi-sub.を用いる
✓PNダイオード→Qsignal
pixel cell
✓rowセレクト(row-wise selection)
read out line
read out line
✓column読み出し(column-wise R/O)
✓select/resetスイッチ
CMOS active pixels (MAPS)
pixel cell
pixel matrix
電荷収集と駆動+信号処理回路が同じ基盤上に配置
DEPFET pixels (セミモノリシック)
row selection and clear
✓sense node (transistor gate)
✓初段FETを完全空乏化したバルク上に配置
✓駆動+信号処理のASICはマトリックスの側面に配置
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
column readout
frame R/O
15
DEPFETピクセル検出器
✓初段FETにPMOS (完全空乏化したバルク上に配置)
• ピクセルサイズ：小
• driftによる電荷収集(fast collection, large signal)
✓Internal gate (IG): n-implant, potential min. for e✓IGに蓄積された電荷に応じてドレイン電流が変化
• low Cdet + amp.→低雑音
✓蓄積電荷をパンチスルー効果によって除去
• 余分なresetが必要(non-commercial process)
source
external
gate
internal
gate
-
✓FETは電荷収集時はOFF
clear gate
• 低消費電力
clear
✓電流信号をフロントエンドASICで処理
• マトリックス駆動用ASIC+信号処理ASIC (CDS)
が必須
drain
>10 yrs R&D Collaboration: Aachen, Bonn, Heidelberg, MPI Munich, Karlsruhe, Plaque, Valencia
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
16
電圧読み出し vs. 電流読み出し
電圧読み出し(ソース)
電流読み出し(ドレイン)
Cgs
Qin on
internal gate
CL
ΔU
Cgs
Cgd
Rf
CL
Cgd
ΔI
電圧は一定
TIA
Qin
I⇠
⇥ gm
Cgd + Cgs
Qin
U⇠
Cg
⌧ = very small
CL · (1 + Cgs /Cgd )
⌧ = 2.2 ⇥
⇠ µs
gm
✓Cgs, Cgdはゲインとスピードのトレードオフ
✓ドレイン電圧が一定なので高速 ✓CLが立ち上がり時間に影響
でリミット)
読み出しが可能
(virtual ground, Rdrainとgate settling time
Belle II用Depfetは電流読み出しを採用
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
17
SICs
ge 0.35µm
mm2
signal
30V
en (36Mrad)
delberg U.
elona U.
DHP (Data Handling Processor)
DEPFETフロントエンドASIC (Belle II)
846
Data reduction and Processing
ARTICLE IN PRESS
P. Fischer et al. / Nuclear Instruments and Methods in Physics Research A 582 (2007) 843–848
" Minimum number of supply, bias and control signals to
devices on a substrate with a resistivity of 150 O cm. The
leakage currents of typically 100 pA=cm2 (at 50 V) are
excellent values. Only ! 10% of the devices have leakage
currents increased by a factor of five. No significant
difference in behavior between normal and thin diodes has
been observed.
simplify wiring on the sensor frame.
マトリックスの駆動/読み出しに3種類のASICを用いる
4.1. HV switch
4. The Switcher3 gate/clear steering chip
In the existing test setups, the control of the gate and
clear signals is achieved with the Switcher2 steering chip.
This chip has been designed 2002 in a 0:8 mm high voltage
technology in order to be able to deliver voltage steps of up
to 30 V for test purposes. This chip is not suited for ILC,
however, for several reasons (geometry, power dissipation,
speed, insufficient radiation hardness). A new chip, Switcher3, has therefore been designed with the following main
goals:
ASIC #2: DCD (Drain Current Digitizer)
• ASICはセンサーサブストレートにバンプボンド DCD-B
" Geometry suited for module construction (slim and
Jelena Ninkovic, MPI HLL Munich
long). Two-dimensional arrangement of bump bonding
pads, 128 channels.
" Voltage steps of up to 10 V, sufficient for operation of
the latest DEPFET devices.
" !"#$%&'()*&+"#(,Minimal dynamic power dissipation, close to zero static
'(0 !,.'%$&,/(
power dissipation.
" Settling time of ! 20 ns for a 9 V step and a load
capacitance of 20 pF.
" Radiation tolerance of at least 1 Mrad.
" Flexible sequencer allowing multiple readout of regions
of interest.
UMC 180nm
Size 3.3 5.0 mm2
Integrated ADC
Noise 40 nA
Irradiation up to 7Mrad
IBM CMOS 90nm
Stores raw data and pedestals
Common mode and pedestal correction
Data reduction (zero suppression)
Timing signal generation
• 10 Mrad (5 yr)
b
9V
6V
9V
9V
6V
c
9V
9V
9V
6V
9V
•
SRAM
•
•
6V
6V
6V
6V
•
6V
9V
6V
3V
3V
9V
AMS high voltage 0.18 um CMOS
Designed by Uni. Heidelberg6V
3V
Size: 3.6×1.5 mm2
6V
3V
3V
contains
additional
logic
for
gated-mode
SwitcherB18 (Gated Mode)
3V
operationReference Manual
6V
in
0V
✓AMS
HV 180 nm CMOS
•
•
✓Univ.
Heidelberg
✓速い駆動信号を供給
(Cd~50 pF)
Requirements to the ASIC
•
0V
Document revision: 3.2
for chip version 2.0
February 17, 2014
FF
Ld2
EnCMC
Ld3
EnInjLoc
T. Kishishita
Cal
VPDAC
SmpLB
SmpRB
r
o
it
n
o
M
EnDKSB
VDC
EnDC
Presamp. CMC
SmpL
AmpOrADC(Global)
CMC CMP CMP
CMC
L
CMC CMP CMP
DAC1
DAC0
DAC
CMC
ADCL
VNSubIn
Receiver
VNSubOut
SmpR
✓256チャンネル
CMC CMP CMP
CMC
Sync(0:1), SmpEn(L:R) Rd01 = Sync0
Strobe Rd23(L:R) = Sync0B & SmpEn(L:R)B
Smp(L:R) = Sync0B & SmpEn(L:R)
V(P:N)Del
WrSignal = Strobe & not sample
Rd01, Wr(0:3), Rd23(L:R)
WrSignal
L
CMC CMP CMP
CMC
ADCR
Decoder
Trans-impedance amplifier
• performance adjustment with DACs
• Each channel with two current mode cyclic ADCs
Figure 2.1: Basic circuits of the analogue channel.
based on current-memory cells
• 80 ns sampling period with 8 bits resolution
16
•
9V
0V
x+3V
0V
3V
x
0V
3V
SRAM
0V
3V
0V
0V
NIM A, v582, p843, 2007
•
stacked-transistor output stage
thin gate oxide transistors for rad.-hard
Design review in Oct. 2014→final submission in 2015!
Prof. Dr. Peter Fischer, Dr. Ivan Perić, Dr. Christian Kreidl
Lehrstuhl für Schaltungstechnik und Simulation
Universität Heidelberg TIPP 2014, 2-6
InjectLoc
EnInjLoc
Config
SerIn, Ck, ShEn
Fig. 4. Simplified schematic of the ‘high voltage’ switch. The operation points for a supply of 9 V are shown for high output (a) and low output (b).
The required gate voltages are generated by AC-coupled SRAM cells.
Fast HV up to 20 V for complete clear within
~20 ns
VPInjSig
TIPP 2014, 2-6 June. Amsterdam
3V
• Fast pulse to drive large line cap. (~50 pF)
✓信号クリア用高電圧信号生成
(~20 V)
•
•
Ld1
EnDC
UMC 180 nm
Designed by Uni. Heidelberg
Size: 3.3×5.0 mm2
Noise: 40 nA
Irradiation up to 7 Mrad
out
SRAM
EnDKS
0V
3V
0V
•
3V
WrSignal
RefIn
SerOut
#1: SWITCHER-B
a
Requirements to the ASIC
• Low-noise
fast settling
current receiver
✓UMC
180 &nm
CMOS
(Rs=200Ω, Cd=50 pF)
✓Univ.
• 10 Heidelberg
M Sample/s
• 256 input channels
✓Current
Receiv. (TIA)+ ADC
ASIC #3
✓low Noise & fastFront-end
settling
DHPT
(Rs=200Ω, Cd=50 pF)
✓10 Mサンプル/s
total area: 0.014 m2
SWITCHER-B
Front-end ASIC
•
Analog frontend and ADC
• センサー部の厚さは75 μm, 周辺部は450Front-end
μm @MPP
DCDB (Drain Current Digitizer for BelleII)
19
One of the biggest challenges for this new chip was the
design of a radiation tolerant analog switch able to operate
at up to 10 V. Irradiations of Switcher2 chips had shown,
that the used HV-devices with thick gate oxides severely
degrade after small (o50 krad) doses already, as expected.
Thin gate devices, on the other hand, do not withstand the
required voltage. The adopted solution is illustrated in
Fig. 4: three stacked 3.3 V NMOS/PMOS devices are used
to pull the output to ground or to the positive switch
voltage, respectively (similar to a circuit in [9]). The
transistors are operated such that under no circumstances
the voltage differences at the terminals exceed the allowed
limit. Fig. 4(a) and (b) shows the required voltages for
high or low output, respectively, for an illustrating supply
voltage of 9 V. The gate voltages of the middle NMOS
(PMOS) can always be held at 3 V (6 V), while the
other gates must be switched between 0 V/3 V, 6 V/3 V
and 6 V/9 V. The required level-shifting is achieved with
SRAM cells which are operated with the corresponding
supply voltages and which are flipped by capacitive
coupling of a 3 V step signal onto the internal storage
node. The feedback inverters in the SRAM cells are current
limited so that flipping is simplified and capacitors of !
200 fF are sufficient. A reset/set signal in the SRAM cells
can be used to define the initial polarity. This level shifting
has no DC current consumption, as required.
June. Amsterdam
20-21 Nov. 2014, 計測システム研究会@J-PARC
13
✓TSMC 65 nm CMOS
TIPP 2014, 2✓Univ. Bonn
✓SW, DCDへのクロック供給
✓Zero-Suppression
✓G-bitデータリンク
18
MAPS-epi テクノロジー
“スタンダード3T”
VRESET
✓センサーと読み出しを同じSiウェハーに形成
AVDD
RE_SEL
ROW_SEL
• commercial CMOSプロセス(安価)
✓low-dopedエピタキシャル層で電荷生成
MAPS-epi
(10-15 um, e.g., AMS 0.35 μm)
COL_LINE
• MIP signal < 1000 e-→低雑音読み出しが課題
-H.V.
✓ eliminate: base levels, 1/f noise, fixed patter noise
✓ do this either offline-> slow or on-chip R&D
✓拡散による電荷収集(~100 ns)
(p-well, sub.による散乱、n-well/epiで収集)
→信号が複数ピクセルに分布
10-15 um
✓NMOSのみをエレキに使用
(n-well/epiがcollection node)
✓小ピクセルサイズ (20-30umピッチ)
→spatial resolution < 2 um
✓Large detector→19.4x17.4 mm2 (1 Mpix)
Meynants, Diericks, Scheffer, SPIE 3410:68-76 (1998)
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
SF
19
STAR PXL sensors
MAPS-epi テクノロジーの現状(@STAR)
Three generations of sensors have been specifically designed for the PXL detector
STAR PXL sensors R&D
illustrates evolution>15
of CPS
development
初のMAPSベースのtracker
(Strasburg+LBNL,
yrs
R&D)
point: Ultimate chip2004-2006
in STAR
First MAPS prototypes for the
STAR PXL detector
ne 2014
n
2008
2011-2012
Full size sensor with
digital readout
Final sensor for the
PXL detector
Complementary detector readout
Sensing
analog
signals
elements
sensor
generations
1st 4 ms integration time
2nd
3rd
ADC
digital
Preamplifier analog
+ CDS
CDS
Digital
signals
ADC
Data
sparsification
DAQ
column level discr. and 0-suppr.
640 µs integration time
< 200 µs integration time
MIMOSA28
C. Hu-Guo
Courtesy of M. Szelezniak, HICforFAIR Workshop 2014
✓ ピクセルサイズ: 20.7 × 20.7 μm2, 厚さ: 50 μm
Architecture (rolling shutter column✓parallel
readout with integrated zero suppression
400 sensors, 356 Mpixels, ~0.15 m2
logic) developed for STAR PXL is well✓suited
twin-well CMOS process
20 toto
90akrad/yr
11to
12µm
2
New architectures are being developed
with
TJ
0.18
CIS
process
(quadruple well process)
✓
2×10
10
n
/cm
eq
MIMOSA28
(ULTIMATE)
✓design
室温で動作
See Marc Winter talk on sensors
for ALICE-ITS upgrade
✓ 積分時間: 185 μs
CPIX14 15-17 September 2014, University of Bonn
T. Kishishita
IPHC
[email protected]
IPHC [email protected]
20-21 Nov. 2014, 計測システム研究会@J-PARC
21
15
20
Basic R.
device
cross-section
(a (2001)
la HV-CMOS/CC
Turchetta,
NIM-A 458:677-689
Deep P Well Implants
many activities: France, UK, US, Italy
(MAPS, CAPS, FAPS …..)
最近のMAPS開発の現状
• PMOS Transistors require an n-well
Hybrid
• PMOS n-well competes with n-well diode
Pixel
MAPS vsdeep-Nwell
Hybrid Pix
MAPS
reducing the charge collection
extended
collecting
electrode
Sensors Te
• To improve charge collection efficiency a deep
implanted
(STM p-well
130 nm is
triple
well cmos)
complete
signal processing chain
Granularity
+
• Reflects
charge
back
into the epitaxial layer
trend: epi→high-R
sub.,
CMOS
electronics
Signal charge & time resolution
Pros
# 
speed
High signalReadout
! full depletion
possible)
Radiation
tolerance
#  Fast ! charge
collection
by drift
#  Small pixels
Charge collection by drift
No
Pavia, Bergamo,(Ref.
Pisa: V.[2])
Re, G. Rizzo et al.
INMAPS
Material budget
Cons+
Yes
INMAPS
# 
+- NMOS in active
++ area !
Only
limited PMOS usage
+-
++
PSD8 Glasgow, 9/5/2008 – N. Wermes, Bonn
Fabian Hügging – University of Bonn – September - 17 - 2013
Yes
“INMAPS”
High voltage
technology
High resistive
substrate
D-MAPS
STANDARD CMOS
epi with deep p-well (RAL, UBirmingham…)
quadrupel well 0.18 um CMOS
to shield the n-wells that contains PMOMS
Monolithic
pixel
on depleted Si
INMAPS
deep-p cannot
be made
too small
Sensor geometrie
James Mylroie-Smith
HV-MAPS
Basic device cross-section (a la HV-CMOS/C
No
Full CMOS in pixel area
In-pixel signal processing
Epi-layer or
bulk CMOS
T. Kishishita
Std. MAPS
HV-MAPS
“LePIX”
Leading institutes: Heidelberg,
Bonn, CPPM, Strasburg
Type9A:!The!collecting!node!loc
Cross-section AVDD AVSS
high resistive sub. (UHeidelberg), CCPD
HV-CMOS 0.18 μm, working up to 1015 cm-2
PW NW
20-21 Nov. 2014, 計測システム研究会@J-PARC
Pros
NW
PW
Cons
NW
21
P
MAPS-SOIテクノロジー(OKI/Rapis)
4/25
✓ハンドルウェハーをセンサーに使用
SOI Monolithic
✓読み出しをBOX層の上に配置
Insulator
(SiO2)
Low R Si
High R Si
pixel sensor
→本当の意味でのモノリシックピクセル…
borrowed from Miyoshi-san, TWEPP-2014
Targets
High-Energy Physics
X-ray astronomy
Material science
Non-Destructive inspection
Medical application
Miyoshi
The features of SOI monolithic pixel sensor
•No mechanical bump bonding. Fabricated with semiconductor process only
• Fully depleted (thick & thin) sensing region
with low sense node capacitance (~10 fF@17 m pixel) high sensor gain
・SOI-CMOS; Analog and digital circuit can be closer smaller pixel size
• Wide temperature range (1-570K)
✓センサー/エレキのカップリング
• Low single event cross section
• Technology based on industry standards; cost benefit →charge injection from CMOS swing
✓BOX層への正電荷蓄積によるVthシフト
4
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC back bias effect →PD…
22
MAPS-SOIテクノロジー@BONN
XFAB 180 nm HV SOI CMOSプロセス
HVPW
Feature size: 180 nm
Supply rail: 1.8 V
p-type bulk, 4 metal layers
Resistivity: ~100 Ω cm
High voltage: ~several 100 V
HVNW
(BOX)
Thickness:
gate oxide: 4.1 nm
BOX: 1 μm
Chip: 300 μm
Distance from Gate to BOX: 3 μm
✓ BOX isolates electronics part from the sensor part p
✓ full depletion possible→ fast & high signals d ⇠ ⇢ · V
✓ full CMOS electronics (CSA, shaper etc. if needed)
✓ theoretically rad-hard (less SEU) + separated with HV-layers
No BOX effects to FETs, sensor optimization is necessary, e.g., Ileak
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
23
HEPに要求される放射線耐性
Innermost pixel layer
BX time
higher lumi. & radiation→smaller pixel
Particle rate
Fluence
Ion. dose
ns
MHz/cm2
neq/cm2 per
lifetime*
kGy per lifetime
LHC(1034cm-2s-1)
25
100
1015
790
HL-LHC(1035cm-2s-1)
25
1000
>1016
5000
SuperBF(1035cm-2s-1)
2
40
ILC(1034cm-2s-1)
350
25
1012
4
RHIC(8 1027cm-2s-1)
110
0.38
1.5 1013
8
T. Kishishita
😨
😨
😃
😃
😃
✓higher rates
✓higher radiation
✓more power
✓more material
✓bigger pixel
100
*lifetime: LHC, HL-LHC for 7yrs,
ILC for 10 yrs, others for 5 yrs
ハイブリッドピクセル
モノリシックピクセル
✓lower rates
✓lower radiation
✓less power
✓less material
✓smaller pixel
3 1012
😃
😃
😨
😨
😨
20-21 Nov. 2014, 計測システム研究会@J-PARC
25
テクノロジーのトレンド
✓
✓
✓
T. Kishishita
3D integration
CCPD (Charge Coupled Pixel Detector)
65 nm CMOS
20-21 Nov. 2014, 計測システム研究会@J-PARC
24
FJ"'(!E>(9"$"7$F'C
adopted from Y. Yarema, Vertex 2007
$H(9B"($F(%B6$8#6"($8"'C(FI(
3D Integration
(CB&C$'3$"(%3$"'836C(IF'(
Detector physicists’ dream…
Tapered TSV process for ATLA
E#$8736 >?
5FV"' >?
G87(
E#$8736 EB$
E#$F N6"7$'F?87C
3?9RF' 0F6$3@" S"@B63$8F?
Tapered Side Wall TSV (Through Silicon Via)
@IZM, Berlin
Al pad
=8@8$36 23H"'
L?36F@ 23H"'
Cu plug
TSV: Main proces flow
U. B%
!"?CF' 23H"'
90 um
Cu pad
5GHC878C$TC ='"3%
./-(234"(563789-(:;<
✓チップを積層(analog,
Chip metal layers
digital)
7
glass supp.wafer
•
TSV formed in the peripheral bond pad
– Pad size of 150µm
Max Si thickness: 100µm
•
etch
TSV formation is a back side processing
– Backside thinning to 90µm stop
– TSV etched BEOL
fromSiO
the2 back side until the BEOL SiO2 stack
•
Front side processing to connect TSV bottom to Al pad
Cu p
– No metal layers in the pad
– ~9µm thick BEOL SiO2 stack technically difficult to etch fro
the TSV opening on the bottom
✓各layerで異なるTechnology
Technologies
are also Important! FE wafer
750 µm
を使用可能 SiGe, opto)
earn(BiCMOS,
the DEPFET/pixel
technologies
✓reduced R, L, and C→speed
ication
fields of analog ASICs...
✓reduced interconnect
power, x-talk
✓reduce pixel size
here,
Cu 7
Laura Gonella – University of Bonn – 26/02/20
first initiative from Fermilab→France, Germany following…
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
need more time…
26
Capacitive Coupled Pixel Detector (CCPD)
520
Fig. 9. 3D view of the g
IEEE TRANSACTIONS ON NUCLEAR S
Fig. 7. Block scheme and photograph of the multi-purpose detector chip.
1st prototype
The input-referred
noise can be
formula
bumpless hybrid approach
CTION
✓“in-house”
✓non-conducting glue
Fig. 10. Photographs of
522
522
521
Fig. 2. Capacitive coupled pixel-detector with passive sensor.
IEEE TRANSACTIONS ON NUCLEAR
SCIENCE
AC
signal
transmiss
IEEE
TRANSA
Pericremain
. un
where we assumed I. matrices,
each chip contains o
not
combine
the
rea
gate-source
capacitance
of
the
CSA
Fig. 8. Two chips are precisely
aligned and glued onto
each other.
Chip A is used only
disabled, Fig. 8.
the parasitic back-side capacitance
The chips are glue
between the readout
electrodes
in
x-direction
is
used
for
the
(PCB
in Fig.
9), c
By taking this into account Bwe
obt
power lines in the top metal-layer. (The additional monolithic
The second identica
pixel-matrix, placed on the chip and shown in Fig. 7, is pre- B and the boards are
sented in [6] and [7].) Only the upper pad-row of the chip is in PCB B allows the
used to read out the CCPD matrices; the bottom-side pads are
Photographs of tw
used for the monolithic pixels.
shown in Fig. 10. T
The detector module is built in the following way. Two chips Fig. 10(b).
from Fig. 7 are precisely aligned and glued onto each other using
a precise flip-chip bonder. This is done in the following way.
V. S
A drop of non-conducting glue is dispensed and spread on the
bottom chip (chip B in Fig. 8) manually. Chip B is then placed
Fig. 11 shows th
on the chuck of the bonder, while chip A is fixed on the bonding pixel. The pixel circ
arm. Mirror-based alignment microscope shows the overlap of are mostly the resu
I. Peric
the projections of both chips. The chuck is aligned using alignare embedded insid
ment markers shown in Fig. 7 and Fig. 8 and the bonding arm The input of ampli
is lowered until the chips touch each other. Pressure (about 1 N using
to the
per chip area) and temperature are applied. In this way, the gap since the input DCbetween the chips is reduced to minimum.
potential of the -w
When the chips are glued in the way describer above, the PMOS transistors, m
sensor- and receiver electrodes form the capacitors for the that the PMOS sour
approximative formula (for noise analysis of pixel detectors
see, for instance, [1])
Depending on the values of ,
(2) the following three cases:
1) Ideal case—the coupling
. Compari
with epi-MAPS with
with
HV-MAPS the feedback capaci- with DEPFET
being the detector
capacitance,
, we
tance of the CSA,
the part of the amplifier input-node capacholds as w
Fig. 5. Active pixel sensor in high-voltage CMOS technology.
Fig.
4.
Active
pixel
sensor
in
low-voltage
CMOS
technology
with
epi-layer.
T.
Kishishita
itance that does 20-21
not originate
from
the detector (for instance the Fig. 6. Active
Nov.
2014,
計測システム研究会@J-PARC
MAPS…
27
pixel
sensor
in DEPFET
technolog
Fig. 5. Active pixel sensor in high-voltage CMOS technology.
the signal
to noise
ratio
(S/N
着任後の抱負
HEPとCMOSテクノロジー
Borrowed from J. Schmitz TIPP 2014
KEK測定器開発室
!""#$%&$213$'$4567,)$144.8./1-9/,)$:;,69<($
+Brilliance of synchrotron sources, # channels in trackers#
HEPでの要求
ASICデザイン
✓小ピクセル化
✓低消費電力
コラボレーション
✓高速信号処理
企業
大学
✓more “intelligence” in each pixel
IndustrialSensor
✓放射線耐性
!technology driven progress"
FE-I4
!"##$%&'()$*+,-./01+$
FE-??
5
applications
Physics65-nm
CMOSが主流になりつつある
New technolog
applications
開発における課題
-基盤となるアナログIP・環境の整備 (ex. MEDIPIX@CERN)
FE-I3
✓Expensive…
✓低電源(😨アナログデザイン)
-先端技術を用いたチップ・センサー開発→CMOS
pixel
(複数プロセスex.
DEPFET←MAPS)
130 nm technology
65 nm technology
250 nm technology
pixel size 400 × 50 µm2
pixel size 250 × 50 µm2
pixel size 125 × 25 µm2
✓ゲート漏れ電流(tunneling)
✓デザインルール増(EGT not arrowed)
-積極的なコラボレーション(ASICの応用範囲を広げる)
80 mil. transistors
~ 500 mil. transistors
✓デザインの複雑化
3.5 mil. transistors
12
(RD53: ATLAS, CMSのpixel FE)
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
28
次世代高エネルギー実験のための65
フロントエンドへの応用@BONN nm CMOS
プロセスを用いたfront-end ASICの開発(1)
M. Havranek
NE#)F#0*<=)292G1
! O.=.0%>#?%'0G#
#######7#.P*)0.L%>#32'#*&*'1#?.@*>#
@
T. Kishishita
Q'
*9
.F
.)
%'
1
130 nm
65 nm
2
250 × 50 µm2
180 × 25 µm
65 nm
O=*#/F%99*/0#
156 × 50 µm2
59 × 25 µm2
0'%)/./02'#.)#$PQ#RR
2 stages
1 stage
NE#)F#0*<=)292G1#
7.8*9#/.J*#SAA#T#EA#UF
7.8*9#/.J*#@EA#T#EA#UF
7.8*9#/.J*#C@E#T#@E#UF ## continuous /dynamic
##
continuous
Comparator
D"E#F.9"#0'%)/./02'/
Z#EAA#F.9"#0'%)/./02'/
VA#F.9"#0'%)/./02'/
E:#CD
Analog power consumption 21.9 µW / pixel 10.6 µW (18 µW) / pixel
!"#$%&'()*+,#-).&*'/.01#23#42))
✓FE-I4と同性能
Analog power density
1.75 mW / mm2 2.36 mW / mm2 (4 mW / mm2)
FE-I4と同程度のアナログ性能でピクセル面積1/4まで縮小可能で
not final design…
@#
@
20-21 Nov. 2014, 計測システム研究会@J-PARC
borrowed from M. Havranek
Technology
WP:XD
Pixel size
Dimensions of analog part
Charge sensitiveCDA#)F#0*<=)292G1#
amplifier
@EA#)F#0*<=)292G1#
#######7#L2)3.=J'%0.2)#'*=./0*'#;:7K.0/#
WP:YY
#######7#A7K.0#/M.30#'*=./0*'7L2J)0*'#
WP:XS
FE-T65-1
#######7#D%/+7K.0#
FE-I4
#######7#$.0Q'#
[O>[I#Q.8*9#WP#<=.7/
Chip design
!2)29.0=.<#;*0*<02'#"#"#"
56789:7;#<#/.)=>*#?.@*>
DK#.)0*G'%0.2)#LCDA#)FM#
- CSA+comparator
- TDAC
- 8 bit counter
- config. register
- mask, HitOr
;AB#CD
$1\'.;#;*0*<02'#
! F)%>2=#?%'0G#
IF%99*'#7.8*9#/.J*#
#######7#HIF#0J)%K>*#.)?J0#L%?%L.0%)L*#
! !2/0#<'.0.<%9#%'*#0=*#.))*'F2/0#7.8*9#9%1*'/
567RS
56789:7;
! $.G=*'#'%;.%0.2)#;2/*/#
#######7#?'2='%DD%K>*#LM%'=*#.)N*L0.2)#
! $.G=*'#9HF.)2/.01,#=.G=*'#=.0#'%0*#
#######7#5OFH#<#0J)%K>*#3**PK%L+#LJ''*)0#
! $>:>$?#.)#~#@A@@#B#CADE#<F:@#/:C#
#######7#8OFH#<#0J)%K>*#0M'*/M2>P#
5*6#7.8*9#3'2)0:*);#<=.7#)**;*;
#######7#L2D?%'%02'##
!"#$%&'()*+,#-).&*'/.01#23#42))
Borrowed from
M. Havranek
borrowed
from M. Havranek
Chip design
✓ピクセル面積1/4
30
nchronous) control logic
次世代高エネルギー実験のための65
nm
CMOS
SAR-ADC
超低消費電力ADCデザイン
DHPT
!"#$%&'($()"*+!,*!-.*
プロセスを用いたfront-end ASICの開発(2)
$%'"%9$/!(*!+<$!'"55"#(*1!0+$80E
M%29$#"%6!"'!
Z2+("*25!
J*0+%39$*+0!+"!
)"993*()2+$]
)"*+%"5!/(1(+25!
0(1*250
Digital output
200
150
100
50
Digital
output
DAC
differential inputs
C7 C6 C5 C4
OUTN
C3 C2 C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
mini ASIC
DAC layout
.
T. Kishishita
(A)
LSB
Bit
Summary of the ADC chip
Bit
Technology
65 nm CMOS, 9 metals
Supply voltage
1.2 V Core & 1.8 V IO
Number of Channels
8 ch (4 ch asynch.+4 ch synch.)
Input range, resolution
0-1.2 V/0.3-0.9 V with 8 bits
40!"um x 70 um (unoptimized)
4( uW@1MS/s, 38 uW@10MS/s
!"#
!"#
Area
(1ch, typical)
!"#
!"#
Power (asynch.)
3D integration, MAPS, photon counting…
Summary
run→新しいアイデアを積極的に取り入れたデザインの試作
(B)
.
Ch
OUTP
.
Asynchronous
logic
Switched
cap. network
.
. .
LSB
dynamic comp.
S&H
LSB
LSB
.
.
0+2+$!#<$%$!+<$!A>F!(0!<(1<!
0
0
0.2
0.4
0.6
0.8
1.0
1.2
5"#:
Analog input voltage [V]
Conventional ADCs are power consuming...
DNL & INL
<$!)282)(+"%0!HG-,.I:
!!!,))3%2)D!"'!+<$!-,.!(0!/$8$*/$*+!"*!+<$!92+)<(*1!"'!
!"#$%&#'()*+(,-#%&.)%!%/0123#45%
!"#$%&#'()*+(,-#%&.)%!%/0123#45%
.K!G
-,.!(0!)"982%$/!+"!G
?LM:!J*! comparator
9$+25!$+)<(*1!2*/!*"(0$!(*!+<$!)282)(+"%!2%%2D:!@<$!4$0+!
→SC
circuit + dynamic
+ small cap.
#6789:%"7;:;%3<;:%
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#6789:%"7;:;%3<;:%
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#6789:%"7;:;%3<;:%
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0!('!+<$!A>F!0<"35/!%$92(*!
DAC layout
with metals
single-ended
mode @ 12.5MS/s 6(7,-'8!9('+*:;!<(201*:=*!>*0=*0=*2-;!<7+-0?!@(+&('(A;!@-,
differential mode
!+<$!)"*=$%0("*:
[INL]
[INL]
2*/!+<$!8%")$/3%$!(0!%$8$2+$/K!
2=$!4$$*!/"*$!'"%!O!4(+0:
#!2!/(1(+25!%$8%$0$*+2+("*!"'!
Bit
[DNL]
Bit
[DNL]
1$:
20-21 Nov.!"#$%!P!2%$2!$''()($*+!,-.!(0!03(+245$!20!'%"*+&$*/!/$0(1*:
2014, 計測システム研究会@J-PARC
5
29
65 nmプロセスの放射線耐性
Core NMOS, leakage current
core NMOS, leakage current
borrowed from CERN group
10
10
Ileak [A]
10
10
10
130 nm
10
106
107
-6
ELT
120 60nm
240 60nm
360 60nm
480 60nm
600 60nm
1000 60nm
10 1 m
10 10 m
-7
-8
65 nm
-9
-10
-11
108
TID [rad]
F.Faccio et al., “Radiation-induced edge effects in deep
submicron CMOS transistors”, IEEE Tr. Nucl. Sci. 2005
10
-12
10
4
10
5
10
6
10
7
10
8
10
9
TID [rad]
✓a rebound effect is visible in 130 nm
65nm has better performance with respect to 130nm: (Plots are in the same scale)
✓all 130 nm devices are peaking at ~100 nA
a rebound effect is visible in 130 nm:
W devices
increase
Ileak by 2 orders of magnitude
all ✓small
130nm devices
are peaking
at ~100nA
✓Ileakdevices
is ~1 nA@136
Mrad
Narrow
increase Ileak
by 3 orders of magnitude
Ileak is ~1nA @136 Mrad
lower Vth shift than 130 nm (core FET)
T. Kishishita
20-21
Nov.
2014,- PH/ESE
計測システム研究会@J-PARC
Sandro
Bonacini
- [email protected]
9 31
Conclusions
ハイブリッドピクセル
needs heavy R&D on sensor materials, ICs and modules, 3D integ.
✓state of art, 技術的には成熟
✓sensorとエレキを別々に選べる
✓rad-hard OK
✓production yieldの問題, アセンブリーが大変, 複雑なオペレーション(many modules)
✓比較的高価 (50-100 EUR/cm2)←innermost layerならOK
✓smaller pixel →50 x 50 um2 with smaller feature-sized technology (65 nm CMOS)
モノリシックピクセル
needs heavy R&D on full CMOS integration, radiation tolerance
✓技術的にはこれから(rad-hard, sensor propertyはprocess optionに依存)
✓大面積を安価に実現できる可能性(commercial CMOS, no bump, <10 EUR/cm2)
✓3D integrationが実現できればより高速かつ、intelligentなpixel検出器が可能
✓Monolithic for ILC; MAPS, DEPFET, new tech. like SOI pix, a-Si:H pixels
Next challenge
✓HL-LHC radiation tolerance up to 1016neq/cm2→新しいセンサー (diamond, 3D)
✓light weight→less power, new cooling, new mechanism
✓data band width: 40MHz→GHz
T. Kishishita
20-21 Nov. 2014, 計測システム研究会@J-PARC
32

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