S i521 4 4 P CI-E X P R E S S 1 ԙ Ƚ 2 ԙ ૂ 3 ԙ 䗉 ࠰ ᰬ 䫕 ਇ ⭕ ಞ ⢯⛯ PCI-Express 1 ԙȽ 2 ԙૂ 3 ԙᇯ 100 MHz с᭥ᤷѨ㺂 ATA (SATA) քࣕ㙍θᐤ࠼䗉࠰ ᰖ䴶㓾ㄥ⭫䱱 ᰬ䫕щ⭞䗉࠰ֵ㜳⺢Ԭᕋ㝐 ᢟ仇щ⭞⺢Ԭᕋ㝐 Ѡ PCI-Express ᰬ䫕 25 MHz Წ։䗉ޛᡌᰬ䫕䗉ޛ ؗਭᇂ᮪ᙝ䈹᮪ ᭥ᤷ I2Cθᑜ䘼䈱ࣕ㜳 ֵ⭞п䀈ᢟ仇᭯ഴᴶཝぁᓜ൦ࠅቇ ⭫ᒨᢦ (EMI) ᢟኋⲺᓜ㤹പ –40 㠩 85 oC 3.3 V ⭫Ⓠ 24 ᕋ㝐 QFN ሷ㻻 䇘䍣ؗᚥφ ৸䰻ㅢ 18 享 ᓊ⭞ 㖇㔒䱺ࣖᆎ۞ ཐࣕ㜳ᢉদᵰ ᰖ㓵⛯ޛ 䐥⭧ಞ ᕋ㝐࠼䞃 ᨅ䘦 Si52144 ᱥᢟ仇ᰬ䫕ֵ㜳 PCIe ᰬ䫕ਇ⭕ಞθਥ֒ѰѠ PCIe ᰬ䫕ⲺⓆȾ 䈛䇴༽ᴿѠ⭞ӄ⭞䗉࠰Ⲻ⺢Ԭ䗉࠰ֵ㜳ᕋ㝐ૂжѠ PCIe ᰬ䫕䗉 ࠰рⲺᢟ仇Ⲻ⺢Ԭᕋ㝐Ⱦ䲚⺢Ԭᕋ㝐ཌθI2C 㕌ぁࣕ㜳䘎ਥ⭞ӄࣞᘷ PCIe ᰬ䫕䗉࠰рⲺⵕȽ㺛ڵᡌњѠᐤ࠼ؗਭрⲺڅ〱Ƚ䗯㕎仇⦽ૂᥥ ᑻȾ䘏〃ࣕ㜳ਥ൞ PCIe ᰬ䫕䗉࠰рᇔ⧦ᴶ֩ؗਭᇂ᮪ᙝૂᴶ֩ EMI ㆴȾ ީӄؗਭᇂ᮪ᙝૂਥ䞃㖤ᙝⲺؗᚥ䈭৸㘹 AN636Ⱦ ࣕ㜳ᯯṼഴ щ⭩䈭ѣ ؤ䇘⡾ 1.2 2/14 ⡾ᵹᡶᴿ © 2014 Silicon Laboratories Si52144 Si5 2144 2 ؤ䇘⡾ 1.2 S i5 2 144 ⴤᖋ ㄖ㢸 享⸷ 1. ⭫≊㿺Ṳ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. ࣕ㜳ᨅ䘦 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Წ։ᔰ䇤 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. OE ᕋ㝐ᇐѿ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. OE ᯣ䀶 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. OE ᰖ᭾㖤փ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. SSON ᕋ㝐ᇐѿ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. ⎁䈋ૂ⎁䠅䇴㖤 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. ᇺᆎಞ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1. I2C ਙ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2. ᮦᦤঅ䇤 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. ᕋ㝐ᨅ䘦φ24- ᕋ㝐 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6. 䇘䍣 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 7. ሷ㻻ཌᖘ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 ᮽẙؤ᭯ࡍ㺞 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 㚊㌱ؗᚥ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 ؤ䇘⡾ 1.2 3 Si5 2144 1. ⭫≊㿺Ṳ Table 1. DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit 3.3 V Operating Voltage VDD core 3.3 ±5% 3.135 3.3 3.465 V 3.3 V Input High Voltage VIH Control input pins 2.0 — VDD + 0.3 V 3.3 V Input Low Voltage VIL Control input pins VSS – 0.3 — 0.8 V Input High Voltage VIHI2C SDATA, SCLK 2.2 — — V Input Low Voltage VILI2C SDATA, SCLK — — 1.0 V Input High Leakage Current IIH Except internal pull-down resistors, 0 < VIN < VDD — — 5 A Input Low Leakage Current IIL Except internal pull-up resistors, 0 < VIN < VDD –5 — — A High-impedance Output Current IOZ –10 — 10 A Input Pin Capacitance CIN 1.5 — 5 pF COUT — — 6 pF LIN — — 7 nH — — 50 mA Output Pin Capacitance Pin Inductance Dynamic Supply Current 4 IDD_3.3V All outputs enabled. Differential clocks with 5” traces and 2 pF load. ؤ䇘⡾ 1.2 S i5 2 144 Table 2. AC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit LACC Measured at VDD/2 differential — — 250 ppm TDC Measured at VDD/2 45 — 55 % CLKIN Rising and Falling Slew Rate TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 — 4.0 V/ns Cycle to Cycle Jitter TCCJ Measured at VDD/2 — — 250 ps Long Term Jitter TLTJ Measured at VDD/2 — — 350 ps Input High Voltage VIH XIN/CLKIN pin 2 — VDD+0.3 V Input Low Voltage VIL XIN/CLKIN pin — — 0.8 V Input High Current IIH XIN/CLKIN pin, VIN = VDD — — 35 uA Input Low Current IIL XIN/CLKIN pin, 0 < VIN <0.8 –35 — — uA TDC Measured at 0 V differential 45 — 55 % TSKEW Measured at 0 V differential — — 50 ps Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 35 50 ps PCIe Gen 1 Pk-Pk Jitter Pk-Pk PCIe Gen 1 0 40 50 ps PCIe Gen 2 Phase Jitter RMSGEN2 10 kHz < F < 1.5 MHz 0 1.8 2.0 ps 1.5 MHz< F < Nyquist Rate 0 1.8 2.1 ps RMSGEN3 Includes PLL BW 2–4 MHz (CDR = 10 MHz) 0 0.45 0.6 ps Long Term Accuracy LACC Measured at 0 V differential — — 100 ppm Rising/Falling Slew Rate TR/TF Measured differentially from ±150 mV 1 — 8 V/ns Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V Crossing Point Voltage at 0.7 V Swing VOX 300 — 550 mV Spread Range SPR — –0.5 — % Modulation Frequency FMOD 30 31.5 33 kHz Clock Stabilization from Power-up TSTABLE — — 1.8 ms Stopclock Set-up Time TSS 10.0 — — ns Crystal Long-term Accuracy Clock Input Duty Cycle DIFF at 0.7 V Duty Cycle Output-to-Output Skew PCIe Gen 3 Phase Jitter Down spread Enable/Disable and Setup Note: Visit www.pcisig.com for complete PCIe specifications. ؤ䇘⡾ 1.2 5 Si5 2144 Table 3. Absolute Maximum Conditions Parameter Symbol Condition Min Typ Max Unit VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 35 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 37 °C/W ESDHBM JEDEC (JESD 22-A114) 2000 — — V UL-94 UL (Class) Main Supply Voltage ESD Protection (Human Body Model) Flammability Rating V–0 Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 6 ؤ䇘⡾ 1.2 S i5 2 144 2. ࣕ㜳ᨅ䘦 2.1. Წ։ᔰ䇤 ྸֵ᷒⭞Წ։䗉ޛθࡏ䇴༽䴶㾷ᒬ㚊䉆ᥥ 25 MHz Წ։Ⱦ Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 25 MHz AT Parallel 12–15 pF Shunt Cap (max) Motional (max) Tolerance (max) Stability (max) Aging (max) 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 2.1.1. Წ։䍕䖳 Წ։䍕䖳ᱥ ppm ⺤ᙝⲺީ䭤ȾѰᇔ⧦ք / 䴬 ppm 䭏䈥θ䈭ֵ⭞с䶘 “ ㅢ 2.1.2. 㢸 䇗㇍䍕䖳⭫ᇯ ” ѣⲺ䇗㇍զ䇗ਾ 䘸Ⲻ⭫ᇯᙝ䍕䖳 (CL)Ⱦ ഴ 1 ᱴ⽰Ⲻᱥֵ⭞њѠᗤ䈹⭫ᇯⲺޮශᲬ։㔉ᶺȾ䈭⌞ᝅᗤ䈹⭫ᇯфᲬ։ᱥѨ㚊ⲺȾ Figure 1. Crystal Capacitive Clarification 2.1.2. 䇗㇍䍕䖳⭫ᇯ 䲚ḽཌ䜞ᗤ䈹⭫ᇯཌθ䘎ਥ㘹㲇ֵ⭞䎦㓵⭫ᇯૂᕋ㝐⭫ᇯ↙⺤൦䇗㇍Წ։䍕䖳Ⱦ∅ж⭫Ⲻםᇯ䜳ᱥфᲬ։Ѩ㚊ⲺȾ њםᙱ⭫ᇯᱥᲬ։䍕䖳⭫ᇯ (CL) рḽ⽰ⲺњكȾ䇗㇍Ⲻᗤ䈹⭫ᇯ⭞ӄֵњ⭫Ⲻםᇯ䍕䖳ㅿȾ Figure 2. Crystal Loading Example ֵ⭞ԛсޢᕅѰ Ce1 ૂ Ce2 䇗㇍ᗤ䈹⭫ᇯٲȾ ؤ䇘⡾ 1.2 7 Si5 2144 Load Capacitance (each side) Ce = 2 x CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL: Წ։䍕䖳⭫ᇯ CLe: ԄᲬ։ᶛⵁֵ⭞ḽٲᗤ䈹⭫ᇯᰬⲺᇔ䱻䍕䖳 Ce: ཌ䜞ᗤ䈹⭫ᇯ Cs: ᵸᮙ⭫ᇯ δ䱬ụε Ci: 䜞⭫ᇯ δᕋ㓵ṼᷬȽਾ㓵ㅿε 2.2. OE ᕋ㝐ᇐѿ OE ᱥ⭞ӄ⭞ૂ⾷⭞䗉࠰ᰬ䫕Ⲻᴿ᭾儎䗉ޛȾ㾷⭞䗉࠰ᰬ䫕θOE ᕋ㝐ᓊѰ䙱䗇儎ъ I2C 䗉࠰ֵ㜳փᓊѰ䙱䗇儎Ⱦ ᴿњ〃⾷⭞䗉࠰ᰬ䫕Ⲻᯯ⌋φሼ OE ࡦ䙱䗇քθᡌሼ I2C ֵ㜳փ䇴㖤Ѱ䙱䗇քȾ OE ᕋ㝐㲳❬ᴿжѠ㖤 100 k ⭫䱱θռԃ䴶㾷ᰬࡱ༺ӄ傧ࣞ⣬ᘷȾ 2.3. OE ᯣ䀶 OE ؗਭᱥ⭞ӄ࠼ࡡੂ↛ૂ↘ڒᔶခ DIFF 䗉࠰ᰬ䫕㙂ެԌᰬ䫕ਇ⭕ಞᤷ㔣ਇ⭕֒⭞ᰬⲺᴿ᭾儎䗉ޛȾሼ OE ؗਭ䇴 㖤Ѱ䙱䗇儎Ⲻᯣ䀶Րֵ Ⲻ↘ڒDIFF 䗉࠰ᰬ䫕ᚘགྷ↙ᑮ䘆㺂Ⱦᰬ䫕ᚘགྷᰬуՐӝ⭕⸣ᰬᡌᔬ䮵Ⲻᰬ䫕㜿ߨȾԄᯣ䀶 ࡦᴿ᭾䗉࠰Ⲻᴶ儎ᔬ䘕у䎻䗽ӂࡦޣѠ䗉࠰ᰬ䫕ઞᵕȾ 2.4. OE ᰖ᭾㖤փ ሼ OE ᕋ㝐䇴Ѱ䙱䗇ք㙂ֵެѰᰖ᭾㖤փᰬθᓊⲺ DIFF 䗉࠰ሼᇂ↘ڒޞθᴶ㓾䗉࠰⣬ᘷ㻡քȾ 2.5. SSON ᕋ㝐ᇐѿ SSON ᱥ⭞ӄ൞ᡶᴿ DIFF 䗉࠰р⭞ –0.5% ᢟ仇Ⲻᴿ᭾䗉ޛȾ䟽ṭ儎ᰬθᡶᴿ DIFF 䗉࠰рൽ⭞ –0.5% ᢟ仇Ⱦ 䟽ṭքᰬθ DIFF 䗉࠰仇⦽уᢟ仇Ⱦ 8 ؤ䇘⡾ 1.2 S i5 2 144 3. ⎁䈋ૂ⎁䠅䇴㖤 ഴ 3 ᱴ⽰ᐤ࠼ HCSL ᰬ䫕䗉࠰Ⲻ⎁䈋䍕䖳䞃㖤Ⱦ Figure 3. 0.7 V Differential Load Configuration ީӄྸ㓾↘ LVDSȽ LVPECL ᡌ CML ؗਭ≪ᒩⲺᐤ࠼䗉࠰Ⲻᔰ䇤θ䈭㿷ᓊ⭞⌞䠀 AN781Ⱦ Figure 4. Differential Measurement for Differential Output Signals (for AC Parameters Measurement) ؤ䇘⡾ 1.2 9 Si5 2144 VMIN = –0.30V VMIN = –0.30V Figure 5. Single-Ended Measurement for Differential Output Signals (for AC Parameters Measurement) 10 ؤ䇘⡾ 1.2 S i5 2 144 4. ᇺᆎಞ 4.1. I2C ਙ Ѱᨆ儎ᰬ䫕ਾᡆಞⲺ⚫⍱ᙝૂࣕ㜳θਥֵ⭞ I2C ਙȾ䙐䗽Ѩ㺂ᮦᦤਙਥֵ⭞〃䇴༽ࣕ㜳θྸ⭞ঋѠᰬ䫕Ⱦф I2C ਙީⲺᇺᆎಞ൞ࣖ⭫ᰬࡓခौѰ唎䇚䇴㖤Ⱦ↚ਙⲺֵ⭞ᱥਥ䘿ⲺȾ㤛䴶㾷ᴪ᭯ᰬ䫕ᇺᆎಞθࡏ䘏〃ᴪ᭯䙐 ᑮᱥ൞㌱㔕ࡓခौᰬ䘑㺂ⲺȾ⭫Ⓠ㇗⨼ࣕ㜳ਠ㜳൞ぁᓅ⁗ᕅс㕌ぁ㙂у㜳൞Ფ䙐䘆㺂⁗ᕅс䘑㺂Ⱦ 4.2. ᮦᦤঅ䇤 ᰬ䫕傧ࣞಞ I2C অ䇤ਥಞⲺߏᆍ㢸Ƚ䈱ᆍ㢸Ƚߏඍૂ䈱ඍᬃ֒Ⱦߏ / 䈱ඍᬃ֒ᱥԄᴶքࡦᴶ儎亰ᓅ䇵䰤 ᆍ㢸 δԄᴶ儎ᴿ᭾փᔶခε θᒬᴿ൞Ֆ䗉ᇂԱᇂ᮪ᆍ㢸Ⲻ↘ڒ㜳࣑Ⱦሯӄߏᆍ㢸ૂ䈱ᆍ㢸ᬃ֒θ㌱㔕ಞਥ 䇵䰤⤢㍘ᕋⲺᆍ㢸Ⱦ ߏඍૂ䈱ඍঅ䇤䈭㿷 㺞 5θߏᆍ㢸ૂ䈱ᆍ㢸অ䇤䈭㿷 㺞 6ȾԄ᭬ಞ൦൶Ѱ 11010110 (D6h)Ⱦ Table 5. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Block Read Protocol Bit 1 Start Slave address—7 bits 8:2 Description Start Slave address—7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code—8 bits 18:11 Command Code–8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count—8 bits 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave 27:21 Slave address—7 bits Data byte 1–8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2–8 bits 46 Acknowledge from slave .... Data Byte/Slave Acknowledges .... Data Byte N–8 bits .... Acknowledge from slave .... Stop 37:30 38 46:39 47 55:48 ؤ䇘⡾ 1.2 Byte Count from slave—8 bits Acknowledge Data byte 1 from slave—8 bits Acknowledge Data byte 2 from slave—8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave—8 bits .... NOT Acknowledge .... Stop 11 Si5 2144 Table 6. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Byte Read Protocol Description Bit 1 Start 8:2 Slave address–7 bits Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code–8 bits 18:11 Command Code–8 bits 19 Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start 27:20 28 Acknowledge from slave 29 Stop 27:21 ؤ䇘⡾ 1.2 Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 12 Description Data from slave–8 bits 38 NOT Acknowledge 39 Stop S i5 2 144 Control Register 0. Byte 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W D2 D1 D0 Name Type 䠃㖤䇴㖤 = 00000000 Bit Name Function 7:0 Reserved Register 1. Byte 1 Bit D7 D6 D5 D4 D3 Name Type DIFF0_OE R/W R/W R/W R/W R/W R/W DIFF1_OE R/W R/W 䠃㖤䇴㖤 = 00000101 Bit 7:3 2 Name Reserved DIFF0_OE 1 0 Reserved DIFF1_OE Function Output Enable for DIFF0. 0: Output disabled. 1: Output enabled. Output Enable for DIFF1. 0: Output disabled. 1: Output enabled. ؤ䇘⡾ 1.2 13 Si5 2144 Register 2. Byte 2 Bit D7 D6 Name DIFF2_OE DIFF3_OE Type R/W R/W D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W D2 D1 D0 䠃㖤䇴㖤 = 11000000 Bit Name Function 7 DIFF2_OE Output Enable for DIFF2. 0: Output disabled. 1: Output enabled. 6 DIFF3_OE Output Enable for DIFF3. 0: Output disabled. 1: Output enabled. 5:0 Reserved Register 3. Byte 3 Bit D7 D6 Name Type D5 D4 D3 Rev Code[3:0] R/W R/W R/W Vendor ID[3:0] R/W R/W R/W R/W R/W D3 D2 D1 D0 R/W R/W R/W R/W 䠃㖤䇴㖤 = 00001000 Bit Name Function 7:4 Rev Code[3:0] Program Revision Code. 3:0 Vendor ID[3:0] Vendor Identification Code. Register 4. Byte 4 Bit D7 D6 D5 D4 Name Type BC[7:0] R/W R/W R/W R/W 䠃㖤䇴㖤 = 00000110 14 ؤ䇘⡾ 1.2 S i5 2 144 Bit Name 7:0 BC[7:0] Function Byte Count Register. Register 5. Byte 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0] Type R/W R/W R/W R/W 䠃㖤䇴㖤 = 11011000 Bit Name 7 DIFF_Amp_Sel 6 DIFF_Amp_Cntl[2] 5 DIFF_Amp_Cntl[1] 4 DIFF_Amp_Cntl[0] 3:0 Reserved Function Amplitude Control for DIFF Differential Outputs. 0: Differential outputs with Default amplitude. 1: Differential outputs amplitude is set by Byte 5[6:4]. DIFF Differential Outputs Amplitude Adjustment. 000: 300 mV 001: 400 mV 010: 500 mV 011: 600 mV 100: 700 mV 101: 800 mV 110: 900 mV 111: 1000 mV ؤ䇘⡾ 1.2 15 Si5 2144 5. ᕋ㝐ᨅ䘦φ24- ᕋ㝐 QFN Table 7. Si52144 24-Pin QFN Descriptions Pin # Name 1 VDD_DIFF 2 OE1 I,PU Active high input pin to enable or disable DIFF1 clock (internal 100 k pull-down). 3 SSON I,PD 3.3 V input for Spread Control (internal 100 k pull-down). 4 VSS GND Ground. 5 OE2 I,PU 6 VDD_DIFF 7 OE0 8 DIFF0 O, DIF 0.7 V, 100 MHz differential clock output. 9 DIFF0 O, DIF 0.7 V, 100 MHz differential clock output. 10 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output. 16 Type Description PWR 3.3 V power supply. Active high input pin to enable or disable DIFF2 clock (internal 100 k pull-down). PWR 3.3 V power supply. I,PU Active high input pin to enable or disable DIFF0 clock (internal 100 k pull-down). ؤ䇘⡾ 1.2 S i5 2 144 Table 7. Si52144 24-Pin QFN Descriptions (Continued) Pin # Name Type Description 11 DIFF1 12 VDD_DIFF 13 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output. 14 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output. 15 DIFF3 O, DIF 0.7 V, 100 MHz differential clock output. 16 DIFF3 O, DIF 0.7 V, 100 MHz differential clock output. 17 VDD_DIFF 18 OE3 I,PU 19 SCLK I 20 SDATA I/O 21 VDD_CORE 22 XOUT O 25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input). 23 XIN/CLKIN I 25.00 MHz crystal input or 3.3 V, 25 MHz clock Input. 24 VSS_CORE 25 GND O, DIF 0.7 V, 100 MHz differential clock output. PWR 3.3 V power supply. PWR 3.3 V power supply. Active high input pin to enable or disable DIFF3 clock (internal 100 k pull-down). I2C SCLOCK. I2C SDATA. PWR 3.3 V power supply. GND Ground. GND Ground for bottom pad of the IC. ؤ䇘⡾ 1.2 17 Si5 2144 6. 䇘䍣 Part Number Package Type Temperature Si52144-A01AGM 24-pin QFN Industrial, –40 to 85 C Si52144-A01AGMR 24-pin QFN—Tape and Reel Industrial, –40 to 85 C Lead-free 18 ؤ䇘⡾ 1.2 S i5 2 144 7. ሷ㻻ཌᖘ ഴ 6 䈪᱄ Si52144 Ⲻሷ㻻䈜㓼ؗᚥȾ㺞 8 ࡍ࠰ᨈഴѣⲺተሮٲȾ Figure 6. 24-Pin Quad Flat No Lead (QFN) Package Table 8. Package Diagram Dimensions Symbol A A1 b D D2 e E E2 L aaa bbb ccc ddd Millimeters Min Nom Max 0.70 0.00 0.20 0.75 0.025 0.25 4.00 BSC 2.70 0.50 BSC 4.00 BSC 2.70 0.40 0.10 0.10 0.08 0.07 0.80 0.05 0.30 2.60 2.60 0.30 2.80 2.80 0.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. ؤ䇘⡾ 1.2 19 Si5 2144 ᮽẙؤ᭯ࡍ㺞 ؤ䇘⡾ 0.1 㠩ؤ䇘⡾ 1.0 ᴪ᯦ㅢ 1 享рⲺࣕ㜳Ⱦ ᴪ᯦ㅢ 1 享рⲺ䈪᱄Ⱦ ᴪ᯦ㅢ 4 享рⲺ㺞 1Ⱦ ᐨᴪ᯦ㅢ 5 享рⲺ㺞 2Ⱦ ᴪ᯦ㅢ 7 享рⲺㅢ 2 㢸Ⱦ ᴪ᯦ㅢ 7 享рⲺㅢ 2.1.1 㢸Ⱦ ᴪ᯦ㅢ 11 享рⲺㅢ 4.1 㢸Ⱦ ᴪ᯦ㅢ 11 享рⲺㅢ 4.2 㢸Ⱦ ᴪ᯦ㅢ 16 享рⲺᕋ㝐䈪᱄Ⱦ ؤ䇘⡾ 1.0 㠩ؤ䇘⡾ 1.1 Ԅ㺞 3 ࡖ䲚Ҽ⒵ᮅᓜ㿺ṲȾ ؤ䇘⡾ 1.1 㠩ؤ䇘⡾ 1.2 20 ᴪ᯦Ҽ㺞 2Ⱦ ᴪ᯦Ҽㅢ 3 㢸Ⱦ ؤ䇘⡾ 1.2 S i5 2 144 ⌞ᝅφ ؤ䇘⡾ 1.2 21 Si5 2144 㚊㌱ؗᚥ Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 ⭫䈓φ1+(512) 416-8500 Ֆⵕφ1+(512) 416-9669 ރ䍯⭫䈓φ1+(877) 444-3032 䈭䇵䰤 Silicon Labs ᢶᵥ᭥ᤷ㖇享φ https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ᒬ⌞߂ᨆӚᢶᵥ᭥ᤷ䈭≸Ⱦ ᵢᮽѣؗᚥ൞࠰⡾ᰬ൞ᡶᴿᯯ䶘ᓊ䈛ᱥ⺤Ⲻθռਥ䳅ᰬؤ᭯θᚋуਜ㺂䙐⸛Ⱦ Silicon Laboratories ሯӄ䭏䈥ૂ䚍╅уᢵԱ䍙Աθъу Րሯഖֵ⭞↚༺ؗᚥ㙂ሲ㠪ⲺԱ᷒䍕䍙ȾਜཌθSilicon Laboratories ሯӄᡶ䘦ࣕ㜳ᡌ৸ᮦⲺ↙ᑮֵ⭞уᢵ䍙ԱȾSilicon Laboratories ؓ⮏ؤ᭯ᮽѣؗᚥⲺᵹθᚋуਜ㺂䙐⸛Ⱦ Silicon Laboratories ሯެӝ⭞ӄԱ⢯ᇐ⭞䙊Ⲻਾ䘸ᙝу֒ԱؓȽ༦᱄ᡌؓ䇷θ Silicon Laboratories Ӝуᢵഖᓊ⭞ᡌֵ⭞ެԱӝᡌ⭫䐥ӝ⭕ⲺԱ䍙Աθ⢯ࡡሯԱૂᡶᴿ䍙Աθऻᤢռу䲆ӄ䰪ᦕඅᡌ䱺ᑜᦕඅᾸу䍕 䍙ȾSilicon Laboratories ӝᵠ䇴䇗Ƚ䇗ࡈᡌᦾᵹ⭞ӄᰞ൞᭥ᤷᡌ㔪ᤷ⭕ળⲺ⭞䙊θᡌ⭞ӄ Silicon Laboratories ӝ᭻䳒ਥ㜳䙖ᡆӰ䓡՚ӗ ᖘⲺԱެԌᓊ⭞ѣȾྸ᷒Ҧᯯ䍣Ҧᡌֵ⭞ Silicon Laboratories Ⲻӝ⭞ӄԱ䶔䇴䇗⭞䙊ᡌᵠ㔅ᦾᵹⲺᓊ⭞ѣθҦᯯᓊؓ䇷 Silicon Laboratories уՐࡦԱ㍘䎊ૂᦕᇩȾ Silicon Laboratories ૂ Silicon Labs ᱥ Silicon Laboratories Inc. ⲺḽȾ ᵢᮽѣެԌӝᡌ⢂〦ᱥ㠠ᡶᴿ㘻Ⲻḽᡌ⌞߂ḽȾ 22 ؤ䇘⡾ 1.2
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