Modeling and Analysis of Circuit Architectures for Emerging

Modeling and Analysis of Circuit
Architectures for Emerging
Technologies
PhD poster day, December 3rd, 2014
Juanchi Wang (PhD II)
[email protected]
Matricola: s200098
ID: 24615
Tutors and Collaborators
• Tutors:
I Prof. Mariagrazia Graziano
I Prof. Maurizio Zamboni
• Collaborators:
I Dr. Marco Vacca
I Dr. Fabrizio Riente
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 2 / 15
Attended classes
Course
Digital and Analog Electronics for
Ultra-broadband networks
Sistemi elettronici a basso consumo
Tecniche avanzate per il progetto di
sistemi elettronici ad alta affidabilità
Etica informatica
CFU
5
Date
18/02/2014
6
18/09/2013
4
17/06/2013
4
20/03/2013
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 3 / 15
Research Context and Motivation
• Newly emerging nanotechnologies are studied for the
purpose of going beyond CMOS technology.
• Among all the promissing candidates, we focus on
I
Nanomagnetic technology, i.e. NML (NanoMagnetic Logic)
I
Nanoarray technology, i.e. NASIC (Nanoscale Application
Specific Integrated Circuits)
A) NASIC basic cell structure - Nanotile. B) Possible implementation technologies for Nanotransistors. C) Three
phase timing diagram.
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 4 / 15
Research Context and Motivation
• Down scaling to few nanometers assures circuit speed and
compactness.
• NASIC employs dynamic circuit style with implicit latching
mechanism, which reduces need of area-consuming
latch/flip-flop components for high density pipelining
architecture.
• PLA-like Nanotiles can exploit the standard design flow or
tools for complex circuits.
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 5 / 15
Addressed Questions and Problems
• For analysis and evaluations on architecture and algorithm
levels, regardless of fabrication details, parametric and
generic models are needed.
• With NML technology well modelized and analyzed with
our previous work, NASIC technology still lacks generic
model for technology implementation analysis and
evaluation.
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 6 / 15
Addressed Questions and Problems
• Following issues should be considered:
I
I
I
I
Signal syncronization
Independence on number of bits
Area evaluation
Power evaluation
• Some architecture blocks are employed for evaluations:
I
I
I
Array Multiplier
Booth Multiplier
Pentium 4 Adder
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 7 / 15
Novel Contributions
N-bit Array Multiplier Implementation
A) Array Multiplier architecture principle. B) Array Multiplier architecture in NASIC implementation. C) Nanotile
structure of 1-bit Full Adder with two AND gates.
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 8 / 15
Novel Contributions
N-bit Booth Multiplier Implementation
A) Booth Multiplier architecture principle. B) Booth Multipler Cell structure. C) Booth Multiplier architecture in NASIC
implementation.
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 9 / 15
Novel Contributions
Pentium 4 Adder Implementation
A) Pentium 4 Adder architecture - Carry Generation. B) Pentium 4 Adder architecture - Carry Select Adder.
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 10 / 15
Novel Contributions
Embedded Area Estimation
AREAnanotile = AREApw + AREAnw
AREAnw = (2NIN + 2) ∗ (2 ∗ NIN + 2 ∗ NOUT + 2) ∗ (Wnw + Dnw )2
AREApw = 2 ∗ (Wpw + Dpw ) ∗ [(2NIN + 2) ∗ (Wnw + Dnw )] + 2 ∗ (Wpw + Dpw ) ∗ [(2 ∗
NIN + 2 ∗ NOUT + 2) ∗ (Wnw + Dnw )]
•
•
•
•
•
•
NIN : Number of inputs.
NOUT : Number of outputs.
Wnw : Width of a nanowire.
Dpw : Distance between two nanowires.
Wpw : Width of a power wire.
Dpw : Distance between two power wires.
No.bits
4
8
16
Area_AM [um2 ]
26.6
217
1735
Area_BM [um2 ]
88
714
8114
Area_P4 [um2 ]
12.5
26.1
59.2
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 11 / 15
Novel Contributions
Embedded Power Evaluation
• Dynamic Power:
Pd =
I
I
I
I
X1
∗ Cw ∗ V 2 ∗ f ∗ SA
2
NWs
Cwire : Switching capacitance on each wire. Cwire = No.NanoFETs ∗ Cgate
V : Supply voltage.
f : Operating Frequency.
SA : Switching activity.
• Static Power:
Ps = No.NWs ∗
V2
ROFF
Power Estimation of some nanotiles: cited from “Nanofabric Power Analysis: Biosequence Alignment Case
of Study”, S.Frache, L.G.Amarù, et.al.
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 12 / 15
Adopted Methodologies
• Technology fabrication constaints consideration.
• Generic VHDL model with detailed logic and timing
operations.
• Emedded area and power calculations.
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 13 / 15
Published and Submitted works
Published:
•
•
•
•
“Biosequences analysis on NanoMagnet Logic”, Wang, J. ; Vacca, M. ; Graziano, M. ; RuoRoch, M.
International Conference on IC Design and Technology (ICICDT) 2013
“NanoMagnet Logic: an Architectural Level Overview”, Vacca, M. ; Graziano, M. ; Wang, J. ; Cairo, F. ;
Causapruno, G. ; Urgese, G. ; Biroli, A. ; Zamboni, M.
Field-Coupled nanocomputing Lecture Notes in Computer Science
“Feedbacks in QCA: a Quantitative Approach”, Marco Vacca, Juanchi Wang, Mariagrazia Graziano Member
IEEE, Maurizio Zamboni,
IEEE Transactions on VLSI Systems
“A Fast Architecture for Finding Maximum (or Minimum) Values in a Set”, Andrea Biroli, Juanchi Wang,
IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2014
Submitted:
•
“A Belief Propagation Polar Codes Decoder Architecture for QCA Technology”, Andrea Biroli, Juanchi
Wang, Giovanni Causapruno, Carlo Condo,
Journal of Circuits, Systems, and Computers (JCSC), Springer
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 14 / 15
Future work
• Further investigation on embedded area and power
estimations.
• Technology- and architecture-level system evaluations.
• Complex architecture examination for technology
comparisons.
Juanchi Wang
PhD poster day, Dec 3rd, 2014
Modeling and Analysis of Circuit Architectures for Emerging Technologies 15 / 15

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