Design Ahead of the Curve 引领技术前沿的设计 微捷码 (Magma)设计自动化有限公司---概述 Magma: Technology, Growth & Performance 微捷码 : 技术,成长和业绩 2 • • • Best Chip Design Technology: Customers rely on Magma for their business-critical ICs. • 广泛深入的应用:利用微捷码工具设计的芯片遍及电话、游戏程序,WiFi,MP3播放器…等 应用 • New Products, New Markets, Rising Revenue: Expanded portfolio, expanded TAM. Guiding to 21%-22% growth this year (FY 2008). • 新产品,新市场,收入增长:扩展产品范围,拓宽市场领域。致力于08财年达到21%-22%的 增长。 • Profitability, Visibility, Predictability: EPS and Op Margin to more than double. Backlog $420+ million entering FY 2008. Meets/beats guidance. • 收益性,可见度,可预测性:每股盈利及营运利润高于两倍的增长。进入2008年财政年度订 单超过4亿2千万美元。达到并超越市场预期。 最优秀的芯片设计技术:客户利用微捷码工具完成其关键IC设计 Pervasive Applications: Magma-designed chips are in cell phones, games, WiFi, MP3 players ... Magma: Success Snapshot (data as of 1/6/2008) Magma:一家成功的公司(截至2008年1月6日的数据) • $60 Market acceptance:高度的市场认同 • World’s top IC companies use Magma for • • Strong team:优秀的团队组成 • 974 employees worldwide. • 974名员工遍及全球 • Emphasis on world-class R&D team and • • • • tech support. 强调世界水平的研发团队和技术支持 More than half the company has master’s or doctorate degrees. 超过半数的员工拥有硕士或博士学位 Financially solid:雄厚的经济实力 • Fiscal 2007 revenue up 8.7 percent over • • • 3 critical designs. 世界顶级IC公司的关键产品使用微捷码的工 具进行设计 2006. Guiding to 21- 22 percent growth in fiscal 2008. 2007财年收入比2006财年增长8.7%。预计 2008年财年目标增长21%-22%。 Profitable with positive operating cash flow. 充沛的现金流支持 $50 $40 $30 $20 $10 $0 季度营收额 (百万美元) IC Design Market Size: $3.4 billion in 2006 IC设计市场规模:2006年3.4亿美元 Custom/ Analog 定制/模拟 Design Capture 捕捉设计$85M Layout & Editing 版图设计 $250M Verification Analysis Sign-off 物理验证,分析 $150M Digital Implementation数字实现 Digital Verification数字验证 电子系统级语言设计Electronic System Language - $180M Synthesis / DFT 综合/测试 $380M Logic Verification 逻辑验证 Emulation, Simulation, Sequential Checking 比对,仿真,连续校验 $650M Physical Implementation 物理实现 Placement & Routing, Floorplanning Prototyping 单元放置及布线,布局,规划 $600M Physical Verification 物理验证DRC, LVS $250M 形式检验Formal Verification - $65M 分析/验证Analysis/Sign-off Timing, Extraction, Noise, Power 时序,RC提取,噪声,功耗 $300M 电路仿真Circuit Simulation - $350M 可制造性设计Design for Manufacturability - RET, DFY, LPC, Physical Design解析度增强技术、针 对良率设计,物理设计 $175M Source: Electronic Design Automation- Consortium 4 来源:电子设计自动化联盟 Market Entry: Place & Route Focus 市场入口:布局布线 • • • • • Key product intro:主要产品介绍: • Blast Fusion, 1999. Primary competitors: 主要竞争者 • Avant! and Cadence. How we changed the game: 我们如何改变局势: • Concurrently addressed timing, area, signal integrity, power and yield. • 同时兼顾时序、面积、信号完整性,功率和 良率 • Optimized performance by enabling design analysis and rapid tradeoffs. • 通过设计分析和快速迭代使性能最优化 $ 425 million* TAM *Market data from EDA Consortium 市场数据来自电子设计自动化联盟 5 Market Expansion: Synthesis 市场拓展:逻辑综合 • • • • Key product intro:主要产品介绍: • Blast Create, 2003. Primary competitor:主要竞争对手 • Synopsys. How we changed the game: 我们如何改变局势: • Integration with physical design. • 整合结构设计 • High capacity – can analyze flat, multimilliongate designs. • 高容量—能够分析处理数百万门设计 • Not relying on wireload models – more accurate than point-tool flows. • 不依赖连线模型-比单点独立工具流程更精准 $ 975 million* TAM *Market data from EDA Consortium 市场数据来自电子设计自动化联盟 6 Moving Beyond Implementation: Verification 超越物理实现:验证 • • • • Key product intro:关键产品介绍: • Quartz DRC/LVS, 2005. Primary competitor:主要竞争对手 • Mentor Graphics. How we changed the game: 我们如何改变局势 • Fast: First truly scalable physical verification tool lets user choose desired turnaround time. • 快速:第一个线性物理验证工具,使设计者 可控制他们的运行时间 • Accurate: Efficient lithographic and CMP model-based checking. • 精准:有效的光刻以及化学机械抛光模式检 查 • Simple: No need for point tools for power and post-design DFM. • 简单:无需为功耗和可制造性设计问题使用 单点独立工具 $ 1.4 billion* TAM *Market data from EDA Consortium 市场数据来自电子设计自动化联盟 7 Expanded Portfolio: Circuit Simulation, Analog 不断增长投资:电路仿真,模拟 • • • • • • Key products intro: 关键产品介绍 • FineSim Pro/FineSim SPICE, 2006. • Titan analog platform, 2008 Primary competitor: 主要竞争对手 • Synopsys (circuit simulation). • Cadence (analog). How we changed the game: 我们如何改变局势: • Circuit simulation: Faster simulation with no compromise on accuracy – natively parallel simulation. Allows simulation of circuits too advanced for traditional SPICE. • 电路仿真:无损精度的快速仿真-内嵌分布式 仿真。允许模拟对于传统SPICE来说过大的电 路 • Analog: Automation of analog IP optimization, process migration, physical verification, physical design chip finishing. Live integration with digital design flow. • 模拟:自动模拟IP优化,过程移植,物理验证 ,物理芯片设计完善,集成与数字设计流程中 $ 2.7 billion* TAM *Market data from EDA Consortium 市场数据来自电子设计自动化联盟 8 Magma Competes Across the IC Design Space Magma在IC设计领域的竞争 Custom/ Analog 定制/模拟 Digital Implementation数字实现 Digital Verification数字认证 Electronic System Language电子系统级语言设计- $180M Design Capture 捕捉设计$85M Synthesis / DFT 综合/测试 $380M Emulation, Simulation, Sequential Checking 比对,仿真,连续校验 $650M Layout & Editing 版图设计 $250M Verification Analysis 物理验证,分析 DRC, Extraction $150M Logic Verification 逻辑验证 Physical Implementation 物理实现 Placement & Routing, Floorplanning Prototyping $600M单元放置及布线,布局, 规划 Physical Verification物理验证 DRC, LVS $250M 形式检验Formal Verification - $65M 分析/验证Analysis/Sign-off Timing, Extraction, Noise, Power $300M时序,RC提取,噪声,功耗 电路仿真Circuit Simulation - $350M 可制造设计Design for Manufacturability - RET, DFY, LPC,Physical Design解析度增强技术、针 Source: Electronic Design Automation- Consortium 对良率设计,物理设计 $175M 9 来源:电子设计自动化联盟 Titan: Analog Platform Expands Capability Titan: 扩展能力的模拟平台 • • Titan gives Magma technology lead in analog design: Titan使微捷码在模拟 设计技术中处于领先 地位: • Analog IP process • • • • • • • 10 migration 模拟IP工艺移植 Full-chip finishing 全芯片实现 True mixed-signal verification 准确的混合信号验证 Unified custom and digital database 统一的定制和数字实 现数据库 Mixed-Signal Design Titan Chip Finishing Semi Companies Know Magma 使用magma的半导体公司 11 Talus Adoption: Implementation Advantage Talus Adoption: 先进的数字实现平台 • NVIDIA: Standardizing on Talus for 45-nm chips. • NVIDIA: 标准采用Talus实现 45-纳米芯片 • Broadcom: “Talus performed very well … gave us confidence to deploy it at Broadcom.” • Broadcom: Talus 性能非常好 …我们Broadcom对采用它很 有信心 • MediaTek: World leader in digital media shortened development with Talus. • MediaTek:数字媒体的世界级 领军厂商因Talus而加速发展 12 Circuit Simulation: FineSim’s Rapid Rise 电路模拟:FineSim的快速增长 • AMD: Names FineSim SPICE the circuit simulator of choice. • AMD:选定使用FineSim SPICE作 为电路模拟工具 • Toshiba: Adopts FineSim Pro and FineSim SPICE for most aggressive designs. Cites “real commercial benefit.” • Toshiba: 在最前沿的设计中采用 FineSim Pro和FineSim SPICE。 认为它带来了“真正的商业收益” • Maxim: FineSim SPICE delivers faster runtime while maintaining SPICE-level accuracy. Magma’s first push into analog mixedsignal. • Maxim: FineSim SPICE带来更 快的运行时间同时保持SPICE级 的精准。Magma首先提供了混合 信号模拟设计。 13 Quartz DRC/LVS: Faster Physical Verification Quartz DRC/LVS: 更快的物理验证 • NVIDIA: Adopts Quartz DRC, Quartz LVS and Quartz DRC Litho to 65nm graphics chips. • NVIDIA:将Quartz DRC, Quartz LVS 和 Quartz DRC Litho应用于65纳米 级图形芯片 • GUC: Completes Taiwan’s first 65-nm tape out. • GUC:完成了台湾的第一 款65纳米产品 • TSMC: Qualifies Quartz DRC for 45-nm. • TSMC: 认定Quartz DRC 适合45纳米应用 14 Partnerships Enable Adoption Magma在行业中众多的合作伙伴用户 15 Staffed to Support World’s Technology Leaders 遍布全球的员工支持各个全球技术领先企业 Eindhoven, The Netherlands R&D Reading, U.K. Sales, AE and R&D San Jose, U.S. Sales, AE, R&D and Corp HQ Austin, U.S. Sales, AE and R&D Durham, U.S. AE and R&D Dallas, U.S. Sales and AE Beijing, China Sales, AE and R&D Herzelia, Israel Sales and AE Seoul, Korea Sales, AE and R&D Shanghai, China Sales and AE Boston, U.S. Sales and AE Los Angeles, U.S. R&D San Diego, U.S. Sales, AE and R&D Meylan, France Sales and AE Munich, Germany Sales, AE and R&D Shenzhen, China AE Noida, India Sales, AE and R&D Mumbai, India Sales, AE and R&D Yokohama, Japan Sales and AE Osaka, Japan Sales and AE Hsinchu, Taiwan Sales, AE and R&D Bangalore, India Sales, AE and R&D Singapore Sales and AE Facilities: 22 Employees: 974 31 Dec 2007 16 Staffing Trend: Most Growth Outside U.S. 员工组成趋势:大部分增长在美国以外 Headcount – Regional and Total (fiscal quarter end) 职工总数-地区和总数(截至第一财季) 930 805 680 21 27 230 163 249 171 202 35 39 38 41 44 44 47 43 87 90 90 89 95 116 32 36 29 35 71 75 425 429 459 474 464 476 486 Q1 FY2007 Q2 FY2007 Q3 FY2007 Q4 FY2007 Q1 FY2008 Q2 FY2008 Q3 FY2008 37 37 82 U.S. 17 46 39 37 27 711 60 874 843 974 Europe Japan Asia-Pac India China R&D Investment History 研发投入回顾 R&D spending, non-GAAP ($ million) 研发投入,非GAAP会计准则(百万美元) $17.1 $16.1 $15.4 $13.3 $15.7 $13.7 $12.6 $11.9 $10.8 $10.8 Jun '05 Sep '05 $10.3 Dec '05 Mar '06 Jun '06 Sep '06 Dec '06 按季度统计 18 Mar '07 Jun '07 Sep '07 Dec '07 R&D Investment History研发投入回顾 R&D spending as percentage of revenue, non-GAAP 研发投入占收入百分比,非GAAP会计准则 30.7% 27.8% 27.1% 32.0% 31.7% 30.4% 30.7% Dec '06 Mar '07 30.7% 29.4% 27.0% 24.9% Jun '05 Sep '05 Dec '05 Mar '06 Jun '06 Sep '06 按季度统计 19 Jun '07 Sep '07 Dec '07 R&D Commitment: Staffing Growing 研发承诺:员工增长 R&D Headcount 研发员工数 453 420 379 391 353 302 280 225 229 Jun '05 Sep '05 248 252 Dec '05 Mar '06 Jun '06 Sep '06 Dec '06 按季度统计 20 Mar '07 Jun '07 Sep '07 Dec '07 Q3 Financial Dashboard Q3财季财政数据 • Revenue $55.7 million • Gross income $49.3 million 营收额 总收益 • Operating income 运营收入 (占营收额88% ) $9.5 million (占营收额17%) • Earnings/share $0.16 • Cash & investments $69.7 million 每股盈利 现金及投资 Non-GAAP results for Fiscal 2008 Q3 (ended January 6, 2008). Arrows show trend from prior quarter. 2008 Q3非GAAP会计准则结果(截至2008年1月6日)向上箭头代表增长趋势 21 Revenue Guidance, FY 2008: 21%-22% Growth 营收额预期,2008财年:21 %-22% 增长 Midpoint, FY2008 guidance (Increased January 31, 2008) Annual Revenue ($million) 年度营收额(百万美元) $215-$217 $178 $164 $146 $114 $75 $46 2002 2003 2004 2005 2006 财政年度(至3月31日) 22 2007 2008 Operating Margin Guidance, FY 2008: 15%-16% 运营利润预期, 2008财年:15%-16%增长 Operating Margin as % of Revenue (non-GAAP) 运营利润占营收额百分比(非GAAP会计准则) 22.8% Midpoint, FY2008 guidance (Increased January 31, 2008) 20.3% 15%-16% 10.3% 5.8% 2004 2005 2006 财政年度 (至3月 31日) 23 2007 2008 EPS Guidance, FY 2008: $0.56 to $0.58 每股盈利预期,2008财年: $0.56 至 $0.58 Diluted Earnings Per Share (non-GAAP) Midpoint, FY2008 guidance (Increased January 31, 2008) 每股摊薄盈利(非GAAP会计准则) $0.62 $0.64 $0.56-$0.58 $0.37 $0.22 2004 2005 2006 财政年度 (至3月 31日) 24 2007 2008 Magma: Technology, Growth & Performance 微捷码 : 技术,成长和业绩 • • • Best Chip Design Technology: Customers rely on Magma for their business-critical ICs. • 广泛深入的应用:利用微捷码工具设计的芯片遍及电话、游戏程序,WiFi,MP3播放器…等 应用 • New Products, New Markets, Rising Revenue: Expanded portfolio, expanded TAM. Guiding to 21%-22% growth this year (FY 2008). • 新产品,新市场,收入增长:扩展产品范围,拓宽市场领域。致力于08财年达到21%-22%的 增长。 • Profitability, Visibility, Predictability: EPS and Op Margin to more than double. Backlog $420+ million entering FY 2008. Meets/beats guidance. • 收益性,可见度,可预测性:每股盈利及营运利润高于两倍的增长。进入2008年财政年度订 单超过4亿2千万美元。达到并超越市场预期。 25 最优秀的芯片设计技术:客户利用微捷码工具完成其关键IC设计 Pervasive Applications: Magma-designed chips are in cell phones, games, WiFi, MP3 players ... 26 Introducing Titan Titan平台发布 World is Mixed Signal…And Integrated世界由混合信号整合而成 Talk交流 Capture捕捉 Create创造 28 Listen聆听 Watch观赏 Mixed Signal = Digital + Analog/Custom混合信号=数字+模拟/定制 The International Technology Roadmap for Semiconductors (ITRS)国际半导体技术发展蓝图 The bleeding edge of analog design is 90nm, and a bunch is still trapped at 130 and 250nm, 5 to 10 year old technology. 模拟设计的前沿特征尺寸是90nm工艺 ,而大量的芯片依然使用130-250nm 或5到10年前的工艺 29 Today, the bleeding edge of digital design is 45nm. Test chips have been done. Flows are being designed NOW. 如今,数字设计的前沿特征尺寸为45nm。测 试芯片已经完成。设计流程在设计中。 Digital Design is Automated, Reusable 数字设计是自动的可重用的 Digital数字 Custom Digital Cells ADC SERDES PLL always @ (posedge sm_clock) begin if (reset == 1'b1) current_state <= 2'b00; else current_state <= next_state; end always @ (current_state or sm_in) begin // default values sm_out = 1'b1; next_state = current_state; case (current_state) idle: sm_out = 1'b0; if (sm_in) next_state = 2'b11; write: sm_out = 1'b0; if (sm_in == 1'b0) next_state = 2'b10; read: if (sm_in == 1'b1) next_state = 2'b01; wait: if (sm_in == 1'b1) next_state = 2'b00; endcase end endmodule Synthesis, Place & Route Turnaround Time 2 Days 综合,布局& 布线 设计周期 2天 30 Synthesized Digital Logic Memory Analog / Custom Design is NOT Automated, NOT Reusable 模拟/定制设计不是自动的,难以重复使用 Custom Digital Cells ADC Analog模拟 SERDES Digital数字 PLL Synthesized Digital Logic Memory IP Process Migration Turnaround Time 6-12 Months IP工艺移植 周期 6-12个月 Integration Synthesis, Place & Route Turnaround Time 2 Days 合成,布局& 布线 周期 2天 31 Turnaround Time 4-8 Weeks 集成 周期 4-8星期 Transcievers, SERDES… Turnaround Time 串行并行转换电路…3-6 Months周期3-6个月 Why?为什么? Analog/Custom Design 模拟/定制设计 System系统设计 Excel, C, Paper, Verilog A/AMS Design C, Matlab, Spice Accuracy ? 精确? Circuit电路设计 Excel, Matlab, Paper… Design Schematic Capture, Spice Automation ? 自动化? Re-use ? 可重用? Physical物理设计 Manual Design & Constraints Design Placement, Routing, Extraction, Spice For every new process node, designs have to be re-created by hand from scratch Ease of Use ? 易于使用? Compatibility ? 兼容性? 每一个工艺节点,设计都要从头重新设计 It’s a Very Hard Problem To Solve.这是一个很棘手的难题 The Kind of Problem Magma Likes to Solve…微捷码善于解决这类难题 32 Magma 2.0: Mixed-Signal Design混合信号设计 Analog IP Process Migration *模拟IP 工艺移植 Integrated Simulation Environment Including Waveform Editor包括波形编 辑器的集成防真环境 Schematic Editor网表编辑器 Layout Editor版图编辑器 Shape-Based, Constraint-Driven Routing基于形状特征, 约束驱动布线 Mixed-Signal Physical Constraints *混合信号物理约束 Digital & Analog Integration数字模拟整合 Integrated Full-Chip LVS, DRC and Extraction集成的全芯 片LVS,DRC 和RC提取 Full-Chip Timing / Signal-Noise Analysis全芯片时序/信号 噪音分析 United Custom and Digital Database统一的定制、数字设计 数据库 Titan: Mixed-Signal Platform混合信号平台 33 * Beta / Limited production now Full Production Q3-08 Driving the Shift to Titan Titan移植 • Accuracy精确 • Automation自动化 • Integration Ease of Use集成 简便易用 • Production-proven FineSim integrated simulation environment 经过量产验证的FineSim 集成仿真环境 • Analog IP process migration automation模拟IP 工艺移植自动化 • Integration to support digital, custom, analog flows seamlessly • 无缝集成支持数字,定制,模拟流程 • • Integration with FineSim, Talus, Quartz DRC/LVS 集成FineSim, Talus, Quartz DRC/LVS • • Faster time to Tapeout 更快的投片 • • Smooth Migration Path 平滑移植路径 • Up to 10x speed and capacity advantage over old solutions • 速度和容量是旧的解决方案的10倍 • Speed and capacity to iterate quickly and close • 高速的迭代和收敛的能力 • OpenAccess compatibility • 兼容OpenAccess数据格式 • Easily transition existing design to Titan • 容易将现有设计移植到Titan 34 Titan: The Only Mixed-Signal Platform仅有的混合信号平台 Embedded Talus 嵌入式Talus 35 Titan: High Speed, High Capacity Layout & Schematic Editor 高速度,高容量版图和网表编辑器 • Responsive all-layer redraw, pan & zoom • 响应所有层的刷新,定位及放大 • Integrated GUI with menus, hotkeys & tear• • • • • • • • off panels 集成的用户界面,菜单热键和面版 Fully scriptable Tcl/Tk interface 完全的Tcl/Tk脚本界面 Cell hierarchy browser 层次化浏览单元 Edit-in-place correct across hierarchy 跨层次在线修改 Full cross-probing: schematics, DRC errors & parasitics • 完全的交叉探测:网表,DRC错误&寄生参数 Example: Layout Editing of 42GB GDSII Design 例如:42GB GDSII版图设计 Full-Chip open全芯片打开 4 min分钟 • • • 36 Redraw刷新 8 sec 8秒 Zoom in by 2放大2倍 4 sec 4秒 Pan time to random points定位到任意点 7 sec 7秒 Titan Accuracy精确性 FineSim SPICE: Fastest SPICE Simulator 最快速的SPICE模拟器 • • • • •37 Unified Single Executable Simulator 单一模拟器 • Native-Parallel™ Technology (NPT) • Native-Parallel™技术(NPT) FineSim SPICE (Full SPICE with NPT) FineSim SPICE (Full SPICE with NPT) • Increased analog SPICE capacity • 模拟SPICE容量增长 • Single-CPU FineSim SPICE 3-10X faster than other SPICE engines • 单CPU FineSim SPICE 仿真3-10倍快于其他SPICE设计 FineSim Pro (Fast SPICE with NPT) • 1-3% SPICE accuracy1-3%SPICE精确度损失 Integrated Analog Simulation Environment 集成的模拟仿真环境 • • FineSim Customer Success FineSim成功案例 • Toshiba, Maxim, Faraday, AMD, SiliconBlue, STARC, Sigma Design... Fully Integrated Custom/Digital Analysis完全集成的定制/数字分析 • Sign-off Quality Analysis • 签核品质的分析工具 • DRC, LVS • Extraction, timing • Noise, power • DFM, yield • Complete Integration完整的集成 • • • • • • 38 Push-button “invocation” 一键完成 Cross-probing debug 交叉探测调试 Fast incremental iteration 快速递增式跌代 Unified, Shape-Based Custom & Chip-Finishing Router 定制设计和全芯片的统一的,基于形状特征的布线器 • Shape-based flexibility基于形状特征的适应性 • Built for modern nm geometries and design sizes • • 基于现代纳米几何形状和设计尺寸 Supports schematic-driven layout 支持网表驱动的版图设计 • • Custom routing constraints 定制设计布线器约束 • Automates critical signal handling • 关键信号的自动处理 • Net length control (min, max, match T-line) • 连线长度控制(最小,最大,适应T-line) • Signal shielding (parallel, tandem, coax) • 信号屏蔽(并联,串联,混合) • Differential pair support • 支持差分对 • Analog-digital global routing • 模拟- 数字布线整体布线 • • • • 39 Ensures timing consistency across digital and custom routing regions 确保时序在数字和定制布线区域的一致性 Speed and capacity to easily handle the largest mixedsignal chips 速度和容量的优势使得可以轻易的处理现在最大的混合信号 芯片 Magma’s Unified Routing System Timing-Driven Global Router Titan Custom Shape Router Talus Digital Router Titan: Open Architecture开放的数据架构 GDS Live Link PDK 3rd Party Tools OA LEF / DEF PCells™ / PyCells™ OA Verilog GDS 40 Volcano SPICE Analog IP Design & Process Migration模拟IP设计及工艺 Original Design Time Process Migration Time Circuit Design 80 days 50 days Layout 60 days 60 days IP process migration requires almost as much circuit design and layout time as the original rev! IP工艺移植要求的电路和版图设计时间几乎与重新设计相当 *Source: Rambus, www.scdsource.com/article.php?id=39 41 Modern Approach to Analog IP Process Migration 先进的模拟IP工艺移植方法 • Write a specification on a computer在一台电脑上创建规范 • Analyze the resulting circuit分析产生的电路 • “Implement and optimize” “实现和优化” • Re-Use it再利用 • Change specifications修改规范 • Change process nodes改变工艺节点 • Do in minutes what would take days and months “the old way”几分钟 内完成,而旧的解决方案需要几天或者数月 Design Constraints设 计约束 Design & Foundry Specific Library设 计及制造特定库 42 Analog IP Process Migration模拟 IP工艺移植 Schematic & Layout Constraints网表及版图 约束 Revolutionary Analog IP Design & Process Migration 革命性的模拟IP设计及工艺移植 Titan AnalogWare Sabio Technology Matlab Specs Standard标 准 Custom定制 Integrated Simulation (FineSim)集成模拟 Mixed-Signal Physical Constraints混合信号物 理约束 Schematic / Layout Editor网表/版图编辑器 Titan Analog Titan模拟优化 Optimization (Circuit & Physical) (电路&物理) Process Models工 艺模型 Process Compiler 工艺编译 器 Sized and Verified Design尺 寸变化及检验设计 PDK 43 Titan: Process Migration Results 过程移植结果 不使用Without Titan 使用With Titan AO AO PCI-E IO driver, 2.5GHz (17 corners) 2 weeks 1 hour Bandgap (33 corners) 3 weeks 5 min 6.4GHz SERDES Linear Equalizer (9 corners) 2 weeks 5 min 1.5GHz, 1V PLL (9 corners) 2 months 1 hour 12 bit pipeline, 100MS, system + op-amps (5 corners) 2 weeks 1 hour Order Of Magnitude Faster Porting While Achieving Equal Or Better Performance 使用Titan可以使速度达到数量级增长,而性能同等于原有性能甚至更好 44 Titan: Integrated Mixed-Signal Platform Titan:集成混合信号平台 • Mixed-Signal Platform混合信号平台 • Embedded Talus嵌入式Talus • Shape-Based Routing基于形状特 • • • 征的布线 • Mixed-Signal Verification混合信号 验证 Analog Block 模拟模块 • Design & Migration设计&移植 Speed and Capacity速度和容量 Compatibility兼容性 • Accommodate Legacy Data兼容已 有数据格式 • OA Compatible OpenAcess数 据格式兼容 45 + + Mixed-Signal Design混合信号设计 46
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