Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6 ACCESS IC LAB ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Outline Concepts of Xilinx FPGA Xilinx FPGA Architecture Introduction to ISE Code Generator Constraints and Reports Configuration Demo and Lab pp. 2 Graduate Institute of Electronics Engineering, NTU Concepts of Xilinx FPGA ACCESS IC LAB ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Electronic Components pp. 4 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Benefits Full-Custom ICs Cell-Based ICs Gate Arrays FPGA Speed ●● ● ● ● Integration Density ●● ● ● ● High-Volume Device Cost ●● ●● ● ● Low-Volume device Cost ● ●● Time to Market ● ●● Risk Reduction ●● Future Modification ●● Development Tool Educational Purpose ● ● ● ●● ●● pp. 5 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Full Xilinx Design Support pp. 6 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Xilinx Products CPLDs and FPGAs pp. 7 Graduate Institute of Electronics Engineering, NTU Xilinx FPGA Architecture ACCESS IC LAB ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU The Conceptual CPLD Architecture pp. 9 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU The Conceptual FPGA Architecture Field-programmable Re-programmable In-circuit design verification Rapid prototyping Fast time-to-market No IC-test & NRE cost H/W emulation instead of S/W pp. 10 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (1/6) pp. 11 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (2/6) Logic and Routing - the CLB tile pp. 12 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6) Logic and Routing – Simplified CLB Structure Two slices in each CLB Each slice contains 2 LUT, 2 Register and 2 Carry Logic. pp. 13 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6) Logic and Routing – Look-Up Tables (LUTs) Combinational logic is stored in Look-up Tables (LUTs) in a CLB. Capacity is limited by number of inputs, not complexity. Delay through CLB is constant. pp. 14 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (4/6) System Interface – Select IOTM Supports multiple voltage and signal standards simultaneously Eliminate costly bus transceivers pp. 15 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (5/6) System Memory – Distributed RAM, Block RAM and External Memory pp. 16 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (6/6) System clock management - DLLs Clock Mirror Multiplication 1 DLL for 2x Combine 2 DLL for 4x Division Selectable division values - 1.5, 2, 2.5, 3, 4, 5, 8, or 16 Phase Shift 0, 90, 180, 270 pp. 17 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-3, VirtexII FPGA Architecture (1/7) pp. 18 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-3, VirtexII FPGA Architecture (2/7) Logic and Routing - the CLB tile pp. 19 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-3, VirtexII FPGA Architecture (3/7) System Interface – Select IOTM 23 different standards supported ! pp. 20 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-3, VirtexII FPGA Architecture (4/7) System Memory –External Memory supports DDR memory pp. 21 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-3, VirtexII FPGA Architecture (5/7) System clock management – DCMs pp. 22 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-3, VirtexII FPGA Architecture (6/7) System clock management – DCMs pp. 23 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spatran-3, VirtexII FPGA Architecture (7/7) Embedded multiplexer pp. 24 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU VirtexII Pro FPGA Architecture pp. 25 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Programmable Logic Evolution pp. 26 Graduate Institute of Electronics Engineering, NTU Introduction to ISE ACCESS IC LAB ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU ISE Philosophy ISE 6.1i Future Xilinx devices Proactive Timing Closure ECS & HDL Bencher & XST Platform Unix: Solaris 2.7/2.8 PC: Win 2000/XP Service Pack http://support.xilinx.com ISE WebPage http://www.xilinx.com/ise pp. 28 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Design Flow in ISE (1/2) Specification Testbench A&B=C Design RTL model A Synthesis C B Pre-Synthesis Simulation CLB Synthesis Post-Synthesis Simulation & Static Timing Analysis Implement A LUT B Reg APR Post-Layout Simulation & Static Timing Analysis Download Download A B C pp. 29 C ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Design Flow in ISE (2/2) pp. 30 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Introduction to Projection Navigator (1/4) pp. 31 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Introduction to Projection Navigator (2/4) Source Windows pp. 32 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Introduction to Projection Navigator (3/4) Processes for current source pp. 33 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Introduction to Projection Navigator (4/4) Processes for current source pp. 34 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Create New Project pp. 35 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Create New Source pp. 36 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU HDL Source File pp. 37 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Text Entry pp. 38 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Language Templates pp. 39 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Synthesis (1/4) XST pp. 40 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Synthesis (2/4) XST Flow pp. 41 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Synthesis (3/4) Synthesis Step pp. 42 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Synthesis (4/4) RTL view pp. 43 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Implementation (1/8) Translate - Merge multiple design files into a single netlist Map - Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs) Place & Route - Place components onto the chip, connect them, and extract timing data into reports pp. 44 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Implementation (2/8) pp. 45 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Implementation (3/8) Translate Core Generator EDIF NCF EDIF EDIF2NGD EDIF2NGD .NGO .NGO .NGO UCF NGDBUILD Logical DRC Check-point .NGO Native Generic Database pp. 46 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Implementation (4/8) Map Optional Guide Files (Files from the last mapping) Optional Constraint File (File from UCF) NCD NGD PCF MDF MAP NGM NCD PCF MDF MRP pp. 47 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Implementation (5/8) Map Property Trim Unconnected Signals If you check this item, the mapping tool will remove the unconnected wire that let the tracing back become hardly. Generate Detailed Map Report If more detailed report is needed, you can check it. (Recommending check it) Use Guide Design File (.ncd) You can refer the last mapping solution so that you maybe get better solution. Use RLOC Constraints Constraints of CLB (default check). Pack I/O Registers/Latches into IOBs If the value chosen Default that pack the register nearby I/O into I/O block. You can also chose only for input or only for output or off. pp. 48 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Implementation (6/8) Place and Route Optional Guide File NCD NCD Single-PAR run NCD PAR PCF P&R Multi-PAR run PAR DIR NCD PAR NCD PAR NCD PAR NCD PAR pp. 49 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Implementation (7/8) Place and Route Property (1/2) Place & Route Effort Level (Overall) Effort Level means the P&R effect result. Using the Higher get the better solution, but spend more time. Starting Placer Cost Table (0-100) Specify a placement initialization value with which to begin P&R attempts. Each subsequent attempt is assigned an incremental value based on the placement initialization value. Place and Route Mode Quick means without timing constraints; Route Only and Re-entrant Route mean P&R must have been run at last once to use this option. Guide File Include the .ncd file. pp. 50 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Implementation (8/8) Place and Route Property (2/2) Use Timing Constraints Include the .ucf file. Use Bonded I/Os If it is checked, signals will be connected to I/O pads. Generate Detailed PAR Report Check the value to generate a detailed PAR report. Generate Post-Place & Route Static Timing Report Check the value to generate post-place & route static timing report. Generate Post-Place & Route Simulation Model Check it for generating required simulation files for ModelSim (*.v and *.sdf). pp. 51 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Download (1/2) pp. 52 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Download (2/2) pp. 53 Graduate Institute of Electronics Engineering, NTU Code Generator ACCESS IC LAB ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU What are Cores? pp. 55 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Benefits of Using Cores pp. 56 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Invoking the CORE Generator GUI pp. 57 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Xilinx Code Generator System GUI pp. 58 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Core Customize Window pp. 59 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Core Data Sheet pp. 60 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Core Generator Design Flow pp. 61 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Link with CodeGen IP (Verilog) pp. 62 Graduate Institute of Electronics Engineering, NTU Constraints and Reports ACCESS IC LAB ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Topics Assign Package Pins (PACE) Assigning Pins Create Timing Constraints The PERIOD Constraints The Pad-to-Pad Constraints The OFFSET Constraints The Constraints Editor Read Report pp. 64 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Constraints GUI (1/2) pp. 65 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Constraints GUI (2/2) pp. 66 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Assign Package Pins (1/6) Start PACE Editor pp. 67 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Assign Package Pins (2/6) PACE Editor GUI pp. 68 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Assign Package Pins (3/6) Method #1 to assign package pins pp. 69 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Assign Package Pins (4/6) Method #2 to assign package pins pp. 70 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Assign Package Pins (5/6) Method #3 to assign package pins pp. 71 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Assign Package Pins (6/6) Method #4 to assign package pins Use text editor to edit .ucf files NET is port name LOC assign pins to specific location pp. 72 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU The PERIOD Constraint pp. 73 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU The Pad-to-Pad Constraint pp. 74 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU The OFFSET Constraint pp. 75 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU The Constraint Editor (1/3) pp. 76 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU The Constraint Editor (2/3) Enter PERIOD and Pad-to-Pad Constraint pp. 77 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU The Constraint Editor (3/3) Enter OFFSET Constraint pp. 78 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (1/12) Create Report Files pp. 79 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (2/12) pp. 80 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (3/12) Example of MAP Report (1/2) pp. 81 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (4/12) Example of MAP Report (2/2) pp. 82 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (5/12) pp. 83 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (6/12) Example of PAR Report (1/2) pp. 84 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (7/12) Example of PAR Report (2/2) pp. 85 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (8/12) pp. 86 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (9/12) Example of Timing Report (1/4) pp. 87 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (10/12) Example of Timing Report (2/4) pp. 88 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (11/12) Example of Timing Report (3/4) pp. 89 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Read Report (11/12) Example of Timing Report (4/4) pp. 90 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Post-layout Simulation .sdf file glbl.v Post layout simulation file testbench simprims Modelsim Result pp. 91 Graduate Institute of Electronics Engineering, NTU Configuration ACCESS IC LAB ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU What is configuration? Process for loading into the FPGA pp. 93 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Configuration Mode (1/4) pp. 94 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Configuration Mode (2/4) Serial Mode pp. 95 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Configuration Mode (3/4) SelectMAP Mode pp. 96 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Configuration Mode (4/4) JTAG or Boundary Scan pp. 97 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU IMACT (1/3) Must double clock “Generate Programming File” before programming FPGA pp. 98 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU IMACT (2/3) pp. 99 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU IMACT (3/3) pp. 100
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