Direct Map
From CPU
0011010
0011 010 100
…
…
Main Memory
(1KB=128Lines)
Yes：Hit
=
Data
010
0011
010
Cache
(64B=8Lines)
Cache Directory
(Tag Memory)
8 entries X (4bit )
ディレクトリは小さくて済む
Direct Map (Conflict Miss)
From CPU
0000010
0000 010 100
…
…
Main Memory
No: Miss Hit
=
010
0011
0000
010
Cache
Cache Directory
(Tag Memory)
010を共通するキャッシュラインは
Conflict Missを起こす
2-way set associative Map
From CPU
0011010
00110 10 100
…
…
Main Memory
(1KB=128Lines)
Yes: Hit
=
Data
0 10
Cache
(64B=8Lines)
10
00110
No
=
00000
Cache Directory
(Tag Memory)
4 entries X 5bit X 2
2-way set associative Map
From CPU
0000010
00000 10 100
0011010
…
…
Main Memory
(1KB=128Lines)
No
=
10
00110
Cache
(64B=8Lines)
1 10
Yes: Hit
=
00000
Cache Directory
(Tag Memory)
4 entries X 5bit X 2
Data
Conflict Missが減る
4-way set associative Map
From CPU
0000010
001101 0 100
0
001101
0011010
…
…
Main Memory
(1KB=128Lines)
=
=
Ｄａｔａ
=
Cache Directory
(Tag Memory)
2 entries X 6bit X 4
000000
=
Cache
(64B=8Lines)
8-way set associative Map → Full Map
0000010
From CPU
0011010
…
…
100
0011010
0011010
Main Memory
(1KB=128Lines)
=
=
=
Ｄａｔａ
=
=
=
Cache Directory
(Tag Memory)
7bit X 8
0000001
=
=
Cache
(64B=8Lines)
Write Through （Hit）
0011010
…
From CPU
…
Main Memory
(1KB=128Lines)
0011 010 100
主記憶も同時に更新
0011
Hit
Cache
(64B=8Lines)
Cache Directory
(Tag Memory)
8 entries X (4bit )
Write Data
Write Through （Miss：Direct Write）
0000010
0011010
…
…
From CPU
Main Memory
(1KB=128Lines)
0000 010 100
主記憶のみ更新
0011
Miss
Cache
(64B=8Lines)
Cache Directory
(Tag Memory)
8 entries X (4bit )
Write Data
Write Through （Miss：Fetch on Write）
0000010
0011010
…
From CPU
…
Main Memory
(1KB=128Lines)
0000 010 100
0011
0000
Miss
Cache
(64B=8Lines)
Cache Directory
(Tag Memory)
8 entries X (4bit )
Write Data
Write Back （Hit）
0011010
…
…
From CPU
Main Memory
(1KB=128Lines)
0011 010 100
Dirty
0011 1
Hit
Cache
(64B=8Lines)
Cache Directory
(Tag Memory)
8 entries X (4bit+1bit )
Write Data
Write Back （Replace）
0000010
0011010
…
…
From CPU
Write
Back
0000 010 100
Main Memory
(1KB=128Lines)
Dirty
0011 10
0000
Miss
Cache
(64B=8Lines)
Cache Directory
(Tag Memory)
8 entries X (4bit+1bit )

Cache File Check 7

Rassegna Stampa - Comune di Vimercate

Euler Winkel

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