uCdragon –YL-LPC2292 UCDRAGON ARM7 BASED BOARD Paolo Bernardi uCdragon –YL-LPC2292 uCdragon –YL-LPC2292 uCdragon –YL-LPC2292 NXP (founded by Philips) LPC2292 LPC2292 Memory model and sections Internal structure Memory model and sections Exceptions time Task IRQ Interrupt handler IRQ Interrupt Second interrupt FIQ Registers FIQ32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc) cpsr cpsr sprsr_fiq spsr_fiq Supervisor32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_svc r14_svc r15 (pc) Abort32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_abt r14_abt r15 (pc) IRQ32 Registers in use r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_irq r14_irq r15 (pc) Registers in use User Mode Undefined32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_undef r14_undef r15 (pc) r0 r1 r2 r1 r2 r3 r3 r4 r5 r4 r5 r6 r6 r7 r7 cpsr spsr_abt cpsr sprsr_fiq spsr_irq r8_fiq r9_fiq r9 r9_fiq r10 r10_fiq r10 r10_fiq r11 r11_fiq r11 r11_fiq r12 r12_fiq r12 r12_fiq r13 (sp) r13_fiq r13 (sp) r14 (lr) r14_fiq r14 (lr) r8_fiq r9 r15 (pc) Return address calculated from User mode PC value and stored in FIQ mode LR spsr_fiq ¨ ¨ Wake-up any useful peripheral Enable interruptions Control idle state power Handling exceptions, including LPC2292 internal and external interrupts ¨ Once launched on the board, the program ¤ Switch-on all leds ¤ In case the button 9 is toggled, an interrupt IRQ exception is raised that ¨ It is a sample program including ¤ Memory structure definition ¤ Initialization of peripheral cores ¤ A main program waiting for interrupts in a idle lowconsumption state ¤ RESET, IRQ, FIQ interrupt handling It works in Flash mode. Sample.s program organization ¨ Sample.s includes the following sections A set of memory organization sections for stack, heap and code segment definition A set of constant values definition including 1. 2. off half of the led set n Programs the internal Timer0 to start counting the Timer0 count ends, a FIQ exception is raised cpsr spsr_fiq Sample.s n Switches ¤ When r14_fiq User mode CPSR copied to FIQ mode SPSR ¨ Sample.s performed functions r13_fiq r15 (pc) cpsr spsr_undef sprsr_fiq Issues in programming the uCdragon ¨ EXCEPTION r8 r8 cpsr cpsr spsr_svc FIQ Mode r0 Program Status Registers ¨ FIQ Interrupt handler Context switching General registers and Program Counter User32 / System user program user program 1. 2. Reset handler including 3. 1. 2. 4. Processor modes Peripheral registers address and, eventually, their content Peripheral core initialization procedure The main program code IRQ and FIQ handlers. Constants for Mode definition 31 28 N Z CV 4 8 I F T STACK/HEAP (DATA) segments 0 Mode Frequencies management constants PIN Selection Pin selection PIN Selection GPIO management constants GPIO management constants Pins may have many functions TIMER0 TIMER0 Timer 0 setup constants Vectored Interrupt controller VIC VIC programming constants External interrupts External interunts constants Power management Interrupt vectors Reset handler – PLL wake-up Reset handler – Pin selection Peripheral bus clock 15MHz Reset handler – Pin selection Reset handler – External interrupt Reset handler – VIC on Reset handler – STACK setup General registers and Program Counter User32 / System FIQ32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc) cpsr cpsr sprsr_fiq spsr_fiq Supervisor32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_svc r14_svc r15 (pc) Abort32 IRQ32 Undefined32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_abt r14_abt r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_irq r14_irq r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_undef r14_undef r15 (pc) Program Status Registers cpsr spsr_svc cpsr spsr_abt cpsr sprsr_fiq spsr_irq cpsr spsr_undef sprsr_fiq Reset handler – STACK setup Main program code Forcing external interrupt 3 IRQ Handler Prepare LR to jump back when finishing IRQ Save registers in the STACK including LR (to enable nested calls/interrupts) IRQ Handler 15*106 [Hz] * 10 [s] = 0X08F0D180 Jump back to main code FIQ Handler
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