aeict/2014/075

National Student Conference On “Advances in Electrical & Information Communication Technology”AEICT-2014
Half Adder, Half Subtractor and Full Adder by Using
Reversible Gates
Akash Goel1,Vineet Monga2, Manish Bhalla3,Arti Saxena4
Electronics and Communication Engineering, PSIT College of Engineering
Kanpur-Agra-Delhi National Highway-2, Bhauti, Kanpur, Uttar Pradesh, India- 209305.
1
[email protected], [email protected],
3
[email protected],[email protected]
Abstract— The Reversible Logic has received great attention
in the past recent years due to its ability in reducing the
power dissipation, the major concern in Digital Designing.
Owing to its unique technique of one-to-one mapping between
the inputs and the corresponding outputs, the reversible logic
gates are now finding profound as well as promising
applications in emerging growing paradigms such as
Quantum computing, Quantum Dot Cellular Automata,
Optical
Computing,
Digital
Signal
Processing,
Nanotechnology and etc. Theimplementationof these logic
circuits into electronic circuitry is based on CMOS
Technology and pass transistor design. The paper presents a
novel design of different Arithmetic and Logic Units such as
HALF ADDER, HALF SUBTRACTOR and FULL ADDER,
using the existing Reversible Gates.
Keywords— Reversible Logic, Reversiblegate,PERES Gate,
NOT Gate, BVF Gate, Garbage.
I.
INTRODUCTION
Reversible Logic:-Now a day computerscan perform a
logic operation for erasing a bit of information. These logic
operations are known as irreversible logic. This erasure
technique is done in a very inefficiently manner, and which
is more than that of energyis dissipated for each bit erased.
If we are continue this logic operation in computer
hardware performance then we have to reduce the energy
dissipated by each logic operation and for improving its
efficiency with which we can erase bit. One of the
alternative methods is reversible logic. It is the logic that
have performed one to one mapping between vectors of
inputs and outputs and thus the vector of input states can be
always reconstructed from the vector of output states.
These logics are known as reversible logic. Even though
the use of reversible logic operations are much useful in the
designing of systems that needs very little power.[1]
This logic provides us an n-Input and n-Output logic
function, which has One-to-One Mapping technique
because of this technique; we can uniquely determine the
output vector from the input vector.
of circuit, judge its limits, i.e. formalized it in terms of
gate-level circuits. For example, the inverter logic which is
performed by NOT gate is be defined as reversible because
it can be undone. The XOR gate is defined as irreversible
because its inputs cannot be reconstructed from an output
value. However, a reversible version of the XOR gate - the
controlled NOT gate (CNOT) - can be defined by
preserved from one of the inputs.
I. REVERSIBLE GATES
A. Peres Gate
Peres Gate is a 3x3Reversible Gate, also called the New
Toffoli Gate, constructed from CNOT and Toffoli Gate. It
has a Quantum Cost of four and described by:
Input Vector = (A, B, C)
Output Vector= (P=A, Q=A B, R=(AB
C)
Figure 1: FPeres/New
Toffoli Gate
IG 1 PERES Gate
B. BVFGate:
The BVF Gate is a 4x4 reversible gate whose quantum cost
is equal to two and described by:
Input= (A, B, C, D)
Output
A B
S= C  D )
Reversible circuits:-One thing keep in mind before
implement reversible circuit are estimate the quantumcost
Department of Electronics & communication Engineering PSIT‖PSIT College of Engineering, Kanpur
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National Student Conference On “Advances in Electrical & Information Communication Technology”AEICT-2014
A B
A
A
PERES
GATE
B
0
BVF
0
A B
G1
GATE
AB
AB
0
G2
Fig 4 Half Adder
Fig 2 BVF Gate
QUANTUM COST= 6
I. QUANTUM COST
The Quantum Cost refers to the cost of the circuit in terms
of the cost of the primitive gates. It is calculated knowing
the number of primitive Reversible Logic Gates required
for realizing the Arithmetic and Logic Circuited) units.
II.
I. HALF SUBTRACTOR
A.
Existing logic
GARBAGE OUTPUTS
The technique of One-to-One Mapping complies that there
must be same number of outputs for the given inputs. The
Garbage Outputs are the unutilized outputs in the
Reversible Logic Circuits that maintain the reversibility but
do not perform any useful operations).
III. HALF ADDER
A.
Existing logic
Fig 5 Half Subtracter
QUANTUM COST= 11
II.
Fig 3Half Adder
QUANTUM COST= 9
The circuitry for the proposed logic is shown in the figure
below. The circuit comprises of NOT, PERES and BVF
GATES.
IV. PROPOSED LOGIC
A
A B
NOT
A
A
GATE
The HALF ADDER is implemented using the PERES and
BVF GATES, where in the number of garbage outputs
being two and represented by G1 and G2, and a constant
input logic ‘0’.
PROPOSED LOGIC
PERES
B
GATE
A B
0
BVF
GATE
AB
AB
0
G1
0
G2
Fig 6 HalfSubtracter
QUANTUM COST= 6
III. PROPOSED LOGIC
In this paper, the proposed full adder circuit consist of two
PERES gate and one BJN Gate. The quantum cost of this
above circuit is 13.
Department of Electronics & communication Engineering PSIT‖PSIT College of Engineering, Kanpur
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National Student Conference On “Advances in Electrical & Information Communication Technology”AEICT-2014
D=A B C
12
Bout= B+C
10
A
B
A
0
PERES
GATE
A B
C
AB  0
A B C
PERES
GATE
0
AB+BC+CA
0
A B C
BVF
GATE
G1
AB+BC+CA
G2
8
Quantum
Cost
6
Fig8 Full Adder
QUANTUM COST= 10
Garbage
Outputs
4
No. of
Constants
Inputs
2
0
IV. RESULT
A. Half adder:
X. TABLE OF COMPARISON:
Fig 9 VHDL output of half adder
Name
of
Circuit
Number of
Gates
Quantum
Cost
Number of
Constants value
Garba
ge
Outp
uts
Half
Adder
2
6
3
2
HalfSub
tractor
2
6
3
2
10
3
B. Full adder:
Full
Adder
3
Fig 10 VHDL output of Full adder
IX. GRAPH OF COMPARISON:
V. DESIGNED FORMULA FOR QUANTUM COST
Department of Electronics & communication Engineering PSIT‖PSIT College of Engineering, Kanpur
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National Student Conference On “Advances in Electrical & Information Communication Technology”AEICT-2014
A. IF NUMBER OF GATES >= NUMBER OF
INPUTS
Quantum cost = (number of inputs + number of
outputs (for single variable))
B. IF NUMBER OF GATES < NUMBER OF
INPUTS FOR EVEN INPUTS
Quantum cost = (2Xnumber of gates – number of
outputs)
C. FOR ODD INPUTS
Quantum Cost = (number of inputs + number of outputs
(for single variable))
VI. CONCLUSION
In this paper, we designed the Half Adder, Half Subtractor
and Full Adder circuits and also simulated these circuits
using VHDL tools, where we improved the quantum cost
and reduced the number of gates. Finally the quantum cost
of all the circuit are 6,6 and 10 respectively, which is the
minimum quantum cost anyone have achieved till now. We
have also given the formula to calculate the Quantum Cost.
REFERENCES
[1]
[2]
[3]
[4]
KomalKumari, ArtiSaxena and Manish Bhalla “ Full adder and
Full subtractor by using Reversible Logic Gates” on soft computing
website: www.scomei.org, (20th feb,2013)
International Journal of Emerging Technology and Advanced
Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO
9001:2008 Certified Journal, Volume 3, Issue 3, March 2013)
H Thapliyal and N Ranganathan, (2009) “Design of Efficient
Reversible Binary Subtractors Based on a New Reversible Gate”,
IEEE Proceedings of the Computer Society Annual Symposium on
VLSI, pp. 229-234.
MajidMohammadi, Mohammad Eshghi, MajidHaghparast and
Abbas Bahrololoom, (2008) “Design and Optimization of
Reversible BCDAdder/Subtractor Circuit for Quantum and
Nanotechnology Based Systems”, World Applied Sciences Journal,
vol. 4, no. 6, pp. 787-792.
Department of Electronics & communication Engineering PSIT‖PSIT College of Engineering, Kanpur
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