ECE 482 CAD TOOLS REFERENCE

ECE 482 CAD TOOLS REFERENCE
Table of Contents
Getting Started… ................................................................................................................. 1
HSPICE & CosmosScope ...................................................................................................... 1
Sample SPICE Netlist File................................................................................................. 1
HSPICE Simulation ........................................................................................................... 2
CosmosScope .................................................................................................................. 2
Cādence Virtuoso ................................................................................................................ 9
Create Library................................................................................................................ 10
Layout Setup ................................................................................................................. 11
Layout............................................................................................................................ 14
Layout with PCELL ......................................................................................................... 20
Extracting a Netlist from Layout ................................................................................... 22
Schematic ...................................................................................................................... 24
LVS ................................................................................................................................. 28
Appendix ........................................................................................................................... 29
Troubleshooting ............................................................................................................ 29
Cādence Hotkeys........................................................................................................... 31
ECE 482 CAD Tools Reference
Getting Started…
You should do your work on an Engineering Workstation (Linux system) by either going
to an EWS lab or by remote connection. Hours, locations and remote settings are
available at http://it.engineering.illinois.edu/ews/.
To set up the correct environment, type the command listed below in a terminal
window.
ece482
This will direct you to the work directory (~/ece482.work) with allocated space for this
course and initialize the environment for HSpice, CosmosScope and Cadence Virtuoso.
HSPICE & CosmosScope
Use a text editor (e.g. gedit) to write the netlist (or you can copy the netlist from HSpice
tutorial below) and save it as a .cir file. For this illustration, we assume the file is saved
as inv.cir.
Sample SPICE Netlist File
This sample file is located at /class/ece482/inv.cir
CMOS Inverter
.lib '/class/ece482/models25' TT
mn1 VSS IN OUT VSS nmos l=0.24u w=0.72u
mp1 VDD IN OUT VDD pmos l=0.24u w=0.72u
cLoad OUT VSS 50fF
vVDD VDD 0 2.5
vVSS VSS 0 0
vIN IN 0 pulse( 0 2.5 100ps 100ps 100ps 2ns 4ns )
.dc vIN start=0 stop=2.5 step=0.01
.tran 1ps 8ns
.option post
.end
The first line of the SPICE stack is always a comment line. Therefore any statements on
this line will be ignored. The .lib line includes the model file, /class/ece482/models25,
which contains device parameters (250 nm process) for simulation.
The next two lines are a NMOS and a PMOS transistor. After the transistor name (which
must begin with m), the source, gate, drain, and bulk nodes are given. Next is the model,
which is either nmos or pmos. The length and width are specified. For a 0.25 𝜇𝑚
process, the minimum gate length is 0.24 𝜇𝑚. For a 0.18 𝜇𝑚 process, the minimum
length is 0.18 𝜇𝑚. Source and drain perimeters and areas can also be specified here.
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A capacitor of 50 fF from node OUT to node VSS is given on the next line.
The two supply nets (vVDD and vVSS) are defined next. Following which, a pulse voltage
source (vIN) is defined from 0 to VDD with 100 ps delay, 100 ps rise time, 100 ps fall
time, 2 ns pulse width, and 4 ns repetition period.
Line .dc indicates a dc sweep of a certain parameter; here the input voltage is swept to
give a voltage transfer curve (VTC). Line .tran indicates a transient analysis with a plot
interval of 1 ps and simulation duration of 8 ns.
Line .option post instructs HSpice to write an output file ending in .tr0 containing the
simulation waveforms. Line .end signifies the end of the SPICE stack.
HSPICE Simulation
HSPICE simulations are run by typing
hspice inv.cir > inv.out
File inv.cir is the name of the SPICE stack file and the output is redirected to a file called
inv.out. The command starting from > and after is not necessary to run HSpice, but then
the output will be visible only in the terminal window. The suffix .cir or .out are just for
clarification when users want to look for some files quickly. If your netlist is in a location
other than your directory in terminal window, just substitute inv.cir with relative
path/inv.cir. You can do the same for output if you do not want to save that in the
current directory. However, other files generated (listed below) are still stored in the
directory shown in terminal window.
inv.ic: Text file containing the circuit initial conditions
inv.st0: Text file containing a summary of the simulation
inv.sw0: Binary file containing dc sweep waveforms (Open this file from CosmosScope to
get the voltage transfer characteristic)
inv.tr0: Binary file containing transient analysis waveforms
CosmosScope
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The waveforms can be viewed using CosmosScope. To start CosmosScope, type
cscope &
The following window will appear.
Click Close to ignore the error message (if applicable).
Transient Simulation Result
Click on File → Open → Plotfiles…, change Files of type to All Plotfiles () and open inv.tr0,
which contains the transient analysis.
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In the inverter Plot File window, plot v(in) by double clicking v(in). v(out) can be plotted
in the same way.
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In order to plot v(in) and v(out) in the same plot, drag v(out) on to v(in) in Graph0
window.
Zoom in to 3 ns and 5 ns by moving the cursor to the x-axis, click 3n, and drag it to 5n.
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ECE 482 CAD Tools Reference
Now zoom out by clicking on the magnifying glass with the square inside it.
DC Simulation Result
To do the dc analysis, first use CosmosScope to open the sweep file inv.sw0. The signal
selection window will come out as the same as in the previous transient analysis.
By highlighting v(in) and then clicking the button Set, v(in) is set to be the X Axis value.
Then highlight v(out) and click the button Plot. The DC curve v(out) vs. v(in) will be
shown, as seen below.
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Click Tools → Measurement Tool to open Measurement window, click the button
besides Measurement, you will see many options. Click General->Slope, select signal to
be v(out), click Apply, a measurement tool/cross-hair which indicates the slope will be
seen in the DC curve.
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Drag the measurement tool to the point where slope is -1, move the mouse onto the
measurement cross hair until its color turns from white to red.
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Right click the cross hair, and select Add Marker → Horizontal Level and Vertical Level.
You can therefore read the necessary noise margin values.
Cādence Virtuoso
To start Cadence Virtuoso, enter the command below after executing ece482 command.
virtuoso &
This opens the Cadence Command Interface Window (CIW). This is the main window of
Virtuoso and most of the message (e.g. design rule check results) will be displayed here.
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ECE 482 CAD Tools Reference
Create Library
In the CIW, go to Tools → Library Manager…
Most of the file management in Cadence is done through the Library Manager. When
you open the Library manager, you should see three columns: Library, Cell, and View. A
cell typically represents a functional block, which could be many different things, such as
a simple circuit (e.g. inverter), a complex circuit (e.g. arithmetic/logic unit), or even an
entire chip. One cell can have multiple views. For example, an inverter cell might have
three views: schematic, layout, and symbol. Symbols let you create a "black box" for the
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ECE 482 CAD Tools Reference
schematic view that can be used in other schematics, which is helpful when managing
complicated designs. A library is a group of related cells.
In the Library Manager click File → New → Library and specify a name (e.g. ece482hw4)
and click OK. In the window that appears, choose Attach to an existing technology
library and click OK.
Select NCSU_TechLib_03d, which is a 250 nm CMOS process, and attach it to our new
library.
Layout Setup
Select the library that you just created, click File → New → Cell View… from Library
Manager. Give the cell a name in the box labeled Cell (e.g. inv), select layout from Type
dropdown list, Click OK.
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ECE 482 CAD Tools Reference
A layout window should automatically open. If it does not, double click layout under the
View column in Library Manager for the cell you created to open it.
Note: If Library Manager Window is not present, clicking Tools→ Library Manager in
CIW will open it.
Before doing any layout, the layout editor must be configured properly. Some important
settings are X/Y snap spacings, minor/major spacings, display level, and gravity. The X/Y
snap spacings determine the size of the grid used for layout. The display level
determines whether instances are shown as black boxes or their actual layout. Gravity
makes the cursor snap to edges and corners that have already been drawn. In most
cases, it's inconvenient.
Click Options → Display from the layout window you just opened, set X and Y snap
spacings to 0.06, set Minor Spacing to 0.3 and Major Spacing to 3, change display level
start to 0 and stop to 32.
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Click Options → Layout Editor and make sure Gravity On option is off.
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Layout
This section is divided into four sections. First, we'll make an NMOS transistor. Second,
we'll make a PMOS transistor. Third, we'll add connections to make them into an
inverter. Fourth, we'll copy the inverter and connect it to the first inverter to make a
buffer and add body connections for the circuit.
The body connections are added last because circuit designers usually use one body tie
for multiple MOS devices to save area.
Draw a NMOS
In the Layers pane on the left side of the layout window, select active layer. Press R on
keyboard to make Create Rectangle the active command and draw a rectangle that's
about twice as wide as it is long. Select the layer nselect and draw a rectangle that
surrounds the active rectangle. These two rectangles create the N+ diffusion that will
become the source/drain of our NMOS.
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Hint: you can use Create Ruler command (press K on keyboard) to draw a few rulers in
the layout editor to measure the size of your drawings.
Select poly layer and draw a narrow rectangle that crosses over the active rectangle, this
rectangle is the gate for our NMOS. Select cc layer and draw two small rectangles, these
rectangles represent the source/drain contacts. Select metal1 layer and draw a
rectangle surrounding each contact (cc) square, these rectangles provide a metal
terminal that connects to the contacts.
Caution: the NMOS is NOT completed yet!
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DRC Check
Run a design rule check (DRC) by going to Verify → DRC… and click OK. DRC errors will
be marked in the layout editor with white lines and an error summary will be available
in the Command Interface Window (CIW). Below is an example which contains three
DRC errors.
********* Summary of rule violations for cell "nmos_min layout" *********
# errors
Violated Rules
1
(SCMOS Rule 3.3) gate enclosure of active: 0.30 um
1
(SCMOS Rule 4.2) select overlap of active: 0.24 um
1
(SCMOS Rule 6.1) active contact size, exactly: 0.24 x 0.24 um
3
Total errors found
To correct gate enclosure of active error, increase the spacing between the top edge of
gate (poly layer) and active region (active layer) to 0.3 𝜇𝑚. To correct select overlap of
active error, increase the spacing between the right edge of active region (active layer)
and select region (nselect layer) to 0.3 𝜇𝑚. To correct active contact size error, set the
size of contact (cc layer) to 0.24 × 0.24 𝜇𝑚.
Use the Stretch (press S on key board) and Move (press M on key board) commands to
edit the layout until the layout gives no DRC errors. The Ruler command (press K on key
board) may be helpful here for measuring distances.
After DRC error correction, the NMOS drawing is complete.
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Tip: Run DRC frequently so you only have to deal with a few errors at a time
Draw a PMOS
Select the nwell layer and draw a large rectangle above the NMOS
Press ESC on keyboard several times so no commands are active. Click and drag around
the NMOS to select all the shapes. Press C on keyboard to activate the Copy command
and click once on the NMOS which selects the reference point of the copy. Click again to
place a copy of the NMOS in the nwell rectangle. Select the nselect rectangle of the
copied NMOS (in the N-well) and press Q to Edit Instance Properties. In Edit Instance
Properties window, change nselect to pselect in the Layer dropdown menu and click OK.
This makes the active rectangle P+, and changes the copied NMOS into a PMOS. Stretch
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ECE 482 CAD Tools Reference
the PMOS active, pselect, poly, and nwell rectangles so the PMOS is twice as wide as the
NMOS. Move the PMOS source/drain contacts to the middle of the diffusion and run
DRC and fix any errors.
Add Connections to Make an Inverter
Stretch the metal1 rectangle on the right side of the NMOS so it overlaps with the
corresponding rectangle on the PMOS.
Hint: You might have to make the active layer unselectable by unchecking its S selection
box it in the Layer pane.
The two diffusions that were just connected are the NMOS and PMOS drains, the metal
line is the inverter's output and the other two diffusions are the sources.
Stretch the NMOS gate so that it connects to the PMOS gate.
Now we are going to create via between metal1 and poly layer. Click Create → Via… and
set Via Definition to M1_POLY to insert a via in the layout. Place this via so that it
overlaps/next-to the left side of the gate between the NMOS and PMOS. This creates a
contact to the NMOS/PMOS gate, which is the inverter's input. This same method can
also be used to make vias to connect metal layers. Don't forget to DRC!
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ECE 482 CAD Tools Reference
Finish the Buffer
Make a copy of the whole inverter and place it to the right of the original. Select the
metal1 layer and use the Path (press P on keyboard) command to connect the output of
the first inverter to the input of the second (you can also draw rectangles separately).
Connect the two NMOS sources together using metal1 paths (this wire will be VSS).
Connect the two PMOS sources together using metal1 paths (this wire will be VDD).
Click Create → Via → M1_P to place a P-well tie next to an NMOS source, click Create →
Via → NTAP to place a N-well tie next to a PMOS source. These two well ties represent
the NMOS and PMOS body ties, respectively. Use Path to connect the NMOS body tie to
VSS and the PMOS body tie to VDD. Select the metal1 net layer (this is different from
the drawing layers near the top of the Layers pane) and use the Label command (press L
on keyboard) to give names to the input/output nodes and VDD/VSS. Type the names in
the window that pops up and click on each net in the order you typed them, these labels
will appear in the final netlist.
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ECE 482 CAD Tools Reference
Layout with PCELL
For an inverter, drawing all the layers may not take a long time since there are only two
transistors involved. However, complex circuits may have hundreds of transistors and
drawing all of them from scratch will take tremendous amount of time (more prone to
making mistakes as well). Thus one can use parameterized cell (PCELL) in his/her layout
for those devices.
Here’s an example to insert a NMOS by using PCELL. Press L on the keyboard in the
layout editor, click Browse button in the Create Instance window. Locate the layout view
of nmos in NCSU_TechLib_tsmc03d in the Library Brower window. Once a device’s
layout view is selected, its corresponding layout is attached to the mouse cursor. Before
placing the device in the layout, enter the correct parameter needed for this device (e.g.
W, L, Multiplier) in the Create Instance window. Left click in the layout editor to place
the device.
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ECE 482 CAD Tools Reference
All transistors (PMOS, NMOS), via (cc, via, via2…) and bulk contacts can be inserted by
PCELL. Below is a NOR gate’s layout using PCELL, it looks very similar to the buffer we
made before without PCELL.
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Extracting a Netlist from Layout
Parasitics, such as parasitic capacitances and resistances of interconnections, may
degrade circuit’s performance and it must be considered during circuit design. By setting
switches (see below), we can extract these parasitic components when extracting a
netlist from layout.
From the layout window, select Verify → Extract. In the window that appears, click Set
Switches → Extract_parasitic_caps, this means the extracted netlist will include parasitic
capacitances of interconnections (e.g. metal wires). Click OK to extract.
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ECE 482 CAD Tools Reference
This creates a new cell view for the buffer named extracted. Open this new cell view
from the Library Manager to view.
To generate a spice netlist for simulation, click Launch → ADE L. In the window that
pops up, click Simulation → Netlist → Create.
Only copy the circuit netlist in the pop up window and change all the references of
tsmc25dP and tscm25dN to PMOS and NMOS for HSpice simulation. Your HSpice circuit
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ECE 482 CAD Tools Reference
file should be similar to the example below (portion highlighted in bold is the extracted
netlist).
CMOS Buffer
.lib 'models25.txt' TT
m0 out n5 vdd vdd PMOS L=240e-9 W=480e-9 AD=288e-15 AS=288e-15
PD=1.68e-6 PS=1.68e-6 M=1
m1 n5 in vdd vdd PMOS L=240e-9 W=480e-9 AD=288e-15 AS=288e-15
PD=1.68e-6 PS=1.68e-6 M=1
c2 vss n5 34.92e-18 M=1
c3 in vss 34.92e-18 M=1
c4 vdd n5 34.92e-18 M=1
c5 vdd in 34.92e-18 M=1
c6 vss n5 84.8448e-18 M=1
c7 out vss 57.2928e-18 M=1
c8 vdd n5 84.8448e-18 M=1
c9 vdd out 57.2928e-18 M=1
m10 out n5 vss vss NMOS L=240e-9 W=480e-9 AD=288e-15 AS=288e-15
PD=1.68e-6 PS=1.68e-6 M=1
m11 n5 in vss vss NMOS L=240e-9 W=480e-9 AD=288e-15 AS=288e-15
PD=1.68e-6 PS=1.68e-6 M=1
vVDD VDD 0 2.5
vVSS VSS 0 0
vIN IN 0 pulse( 0 2.5 100ps 100ps 100ps 2ns 4ns )
.dc vIN start=0 stop=2.5 step=0.01
.tran 1ps 8ns
.option post
.end
Note: Simulation time for a large circuit (e.g. 100+ transistors) with extracted parasitic
capacitances may be long since parasitic components complicate the Spice netlist. To
reduce simulation time, you can first simulate your circuit without parasitic components
to verify the basic functionality. Once the circuit’s functionality has been confirmed, you
can simulate it with parasitic components to measure its timing.
Schematic
This part of tutorial covers schematic drawing in Virtuoso, which is useful for complex
circuit design.
Select the library that you just created and create a new cell view by File → New → Cell
View in Library Manager with schematic Type. A schematic window should automatically
open. If it does not, double click on schematic under the View column to open it
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ECE 482 CAD Tools Reference
In the schematic editing window top menu, click Create → Instance… (press I on
keyboard) to open Component Browser. Select NCSU_Analog_Parts from the dropdown
list in the Library. Select N_Transistors and nmos4 in Filter menu to select 4-terminal
NMOS transistor symbol.
Now you can see the NMOS symbol attached in your cursor, and a window pops up,
where you can change the parameters of this NMOS transistor. Left-click to put that
symbol on the schematic editor window. To instantiate PMOS, you can select
P_Transistors and pmos4 in Filter menu.
To change transistor size, click instance (pmos4 or nmos4) and click Edit → Properties →
Objects… (Hot key: Q) in the top menu. In the pop-up window of Edit Object Properties,
you can size your transistor.
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To add wire to connect transistors, click Create → Wire (narrow), (Hot key: W) in the
left-hand side. Use this wire to connect each port of the symbols.
To add pins, click Create → Pin… in the top menu (Hot key: P). In the pop-up window,
specify Pin Names and Direction from dropdown list. Always set the Direction of supply
pins (e.g. VDD, VSS) to inputOutput, set the Direction of input pins as input, output pins
as output.
When schematic editing is finished, click File → Check and Save or click the third icon
Check and Save from the left on the top tool bar. If you have any errors or warning,
please check messages in the CIW window. The complete inv0 schematic is shown
below.
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Symbol Definition
Now we want to make a symbol for this inverter so that we do not need to draw the
transistors again when this inverter is needed in some other circuit.
Click Create → Cellview → From Cellview…, select Tool Type as schematicSymbol and
click OK in the pop up window. In the following window select your location of the pins
on the symbol, and click OK.
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The symbol window pops up. The next time you want to add this inverter symbol, do the
same as you do for NMOS and PMOS transistors, except that you need to select the
library you created with the inverter from the drop list.
Please feel free to explore the tool bar and menus for more options. You can also refer
to the appendix where more hotkeys are listed.
LVS
In order to use Layout Versus Schematic (LVS), you must have a cell with schematic,
layout and extracted layout. In the layout or extracted view window, click Verify →
LVS… to open LVS setup window.
Check schematic and extracted in the checkbox, and type Library, Cell, View names (You
can do this by clicking Browse button to select the proper cell views). If you want to
check the transistor sizes, check Device Fixing in LVS options.
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Press Run button at the bottom. If the layout matches the schematic, you will see a popup message that indicates The LVS job completed, the net-lists match. If those two are
not matched, the pop-up message will say The net-lists failed to match. In this case,
return to the LVS window and click the Output button for details. You can also click Error
Display button, which highlights (with pink squares) the mismatch part on your
schematic or your extracted view, depending on the window you have opened.
Appendix
Troubleshooting
Cadence Library Not Found in Library Manager
If you start Cadence and cannot find your previously created libraries in the Library
Manager, you need to add those libraries manually. Click Tools → Library Path Editor…
in Command Interface Window (CIW). In Library Path Editor window, click Edit → Add
Library…
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Browse to the directory, which contains your libraries and select the one you need to
add in the Library column, then click OK.
Now the added library should be listed in the Library Path Editor, be sure to save (File →
Save) your change before close it.
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Cadence License Not Available
You may get an error message indicates there’s the license for a certain tool is
unavailable, usually this problem can be resolved by clicking Yes or Always option in the
dialog window.
Cādence Hotkeys
Hot keys can be freely configured by a Bindkeys setting. But the list of hot keys below
shows the “commonly” used ones. These are applied as a default set when you run
Cadence on your EWS.
Layout Editor
f: zoom to fit layout into the full window
ctrl + z: zoom in
shift + z: zoom out
m: move
s: stretch
r: draw rectangle
c: copy
i: add instance
shift+f: show instances’ detailed layout
ctrl+f: show instances as simple red boxes
k: ruler on, shift+k: ruler off
u: undo, shift+u: redo
q: property
x: descend into an instance
b: back from an instance
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m (select objects), mouse right-click: rotate an object counterclockwise
(click a rectangle), shift+c, draw a rectangle: chop
(select multiple rectangles), shift+m: merge
(ctrl)+d: deselect everything selected
Schematic Editor
f: zoom to fit schematic into the full window
ctrl+z: zoom in, shift+z: zoom out
m: move
s: stretch
c: copy
i: add instance
w: add wire
p: add pins
q: property
u: undo, shift+u: redo
(shift)+x: descend into an instance (press ‘shift’ for editing)
(shift)+b: back from an instance (press ‘shift’ for editing)
m (select objects) mouse right-click: rotate an object counterclockwise
(ctrl)+d: deselect everything selected
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