1. No category

Novena PVT2-A

1
2
3
4
5
6
7
8
Power sequencing
A
A
Novena PVT2-A
B
B
I2C mappings:
C
C
addresses are already shifted left by one to accommodate r/w bit
i.e., address is expressed as the write address
I2C1: 10k pull-up
SMBus functions (optional)
MMA8452 (0x38) (optional)
SO-DIMM identification (0xA0)
FPGA (optional)
SO-DIMM temp sensor (0x30) (optional)
STMPE610 (0x88) (optional)
Gas gauge and charger via SMB (on battery board)
PCF8523 RTC (0xD0)
P1.8V_SW4 has option to power VTT
Use this option to lower VTT source to 1.0V to save power
I2C2: 1.8k pull-up
HDMI DDC (0xA0, 0x74)
expansion header
FPGA (optional)
PMIC (0x10)
changes on table:
P1.8V_VGEN3 micbias gen option
(reprogram to 3.0V before using)
D
D
I2C3: 2.2k pull-up
LCD EDID (0xA0)
ES8283 (0x22)
FPGA (optional)
Utility EEPROM (0xAC)
U_02cpu_power
U_06cpu_soc
U_10ethernet100
U_14audio
02cpu_power.sch
06cpu_soc.sch
10ethernet100.sch
14audio.sch
U_03cpu_sodimm
U_07sdcard
U_11ethernetGbit
U_15fpga
03cpu_sodimm.sch
07sdcard.sch
11ethernetGbit.sch
15fpga.sch
U_04pwr_pmic
U_08usb
U_12mPCIe
U_16gpio_misc
04pwr_pmic.sch
08usb.sch
12mPCIe.sch
16gpio_misc.sch
U_05pwr_input
U_09sata
U_13hdmi_lcd
05pwr_input.sch
09sata.sch
13hdmi_lcd.sch
E
E
1
2
Copyright 2014 Andrew "bunnie" Huang
Sheet: /
File: 01docmap.sch
PVT2-A
Title:Novena
01docmap
3
4
Copyrights:
CC-BY-SA 3.0
5
Patents: Apache
2.0
6
Size: B
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
7
Rev:
Id: 1/16
8
1
2
3
4
5
6
7
8
9
10
11
Note: 22uF, 6.3V 0603 cap is TDK C1608X5R0J226M
A
G
H
1
1
2
1
1
2
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
22uF, 6.3V, X5R, 20%
i.MX6 Q,DL,S: short
1
1
2
2
1
1
2
2
VDDSOC_CAP
+VDD
1
1
2
2
C42C
2
1
1
C37C
2
1
1
C36C
2
0.22uF, 6.3V, X5R 10%
i.MX6 D: short
B
0.22uF, 6.3V, X5R 10%
1
i.MX6 Q,DL,S: open
22uF, 6.3V, X5R, 20%
GND_20
2
2
C29C
+GND
C35C
1
1
1
2
2
1
1
2
2
1
1
C26C
2
1
1
2
0.22uF, 6.3V, X5R 10%
2
1
1
2
0.22uF, 6.3V, X5R 10%
2
1
1
2
2
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
2
2
1
1
2
1
1
2
i.MX6 D: open
22uF, 6.3V, X5R, 20%
1
1
2
1
1
2
GND_24
2
1
1
1
2
2
1
2
2
C
22uF, 6.3V, X5R, 20%
1
C65C
1
0.22uF, 6.3V, X5R 10%
GND_22
2
0.22uF, 6.3V, X5R 10%
C60C
+GND
2
1
1
2
0.22uF, 6.3V, X5R 10%
2
2
2
1
1
C66C
C55C
GND_12
22uF, 6.3V, X5R, 20%
+GND
2.2uF, 25V, 10% X5R
2
+3.3V
C69C
+GND
GND_9
+GND
C54C
VDD_SNVS_CAP
C70C
2
+VDD
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
1
1
2
0.22uF, 6.3V, X5R 10%
2
1
1
2
1
1
2
2
2
1
1
2
2
1
1
1
1
2
2
2
0.01uF, 10V, X5R,0.22uF,
10% 6.3V, X5R 10%
0.01uF, 10V, X5R,0.22uF,
10% 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
2
1
1
2
2
C64C
supplied by internal regulator
VDD_HIGH_CAP
C72C
C53C
D
0.22uF, 6.3V, X5R 10%
P2.5V_VGEN5_3
1
C73C
2
2
NVCC_EIM0
K19
NVCC_EIM1
L19
NVCC_EIM2
M19
0.22uF, 6.3V, X5R 10%
+GND
VDD_HIGH_CAP_2
+VDD
C74C
1
1
K7
GND_25
0.22uF, 6.3V, X5R 10%
NVCC_MIPI
+2.5V
1
N7
NVCC_CSI
2
GND_7
2
+GND
0.22uF, 6.3V, X5R 10%
P2.5V_VGEN5
+2.5V
1
1
C25C
2
2
0.22uF, 6.3V, X5R 10%
2
NVCC_GPIO
P7
GND_10
+GND
2
NVCC_ENET
R19
1
1
C75C
22uF, 6.3V, X5R, 20%
E
P3.3V_DELAYED_2
G14
NVCC_NANDF
G15
1
1
1
1
2
2
GND
2
2
1
2
2
0.22uF, 6.3V, X5R 10%
1
1
0.22uF, 6.3V, X5R 10%
C85C
+3.3V
0.22uF, 6.3V, X5R 10%
P3.3V_DELAYED_3
GND_11
+GND
0.22uF, 6.3V, X5R 10%
P3.3V_DELAYED_4
C86C
+3.3V
F
2
2
1
1
NVCC_SD3
C79C
+3.3V
+GND
2
0.22uF, 6.3V, X5R 10%
G17
2
GND_5
NVCC_SD2
0.22uF, 6.3V, X5R 10%
2
GND_27
+GND
2
2
1
2
2
2
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
P3.3V_DELAYED_6
C84C
+3.3V
+GND
10uF, 10V, X5R, 20%
1
G16
C82C
+2.5V
1
NVCC_SD1
+GND
P2.5V_VGEN5_2
C28C
1
G18
0.22uF, 6.3V, X5R 10%
GND_28
NVCC_RGMII
C78C
GND_3
+GND
2
2
2
2
1
1
C80C
C77C
GND_2
+GND
1
C81C
1
E8
NVCC_PLL_OUT
GND_4
+GND
1
1
C76C
1
NVCC_PLL_OUT
GND_26
0.22uF, 6.3V, X5R 10%
+GND
P3.3V_DELAYED_5
C87C
1
+3.3V
2
GND_8
+GND
0.22uF, 6.3V, X5R 10%
1
2
C88C
1
NVCC_JTAG
1
J7
GND_6
2
F
NVCC_LCD
2.5V
P3.3V_DELAYED
+GND
C8
A5
B5
GPANAIO
FA_ANA
VDD_FA
2
E
P19
C63C
10uF, 10V, X5R, 20%
supplied by internal regulator
1
A4
A8
AA10
AA13
AA16
AA19
AA22
AA7
AB24
AB3
AD10
AD13
AD16
AD19
AD22
AD4
AD7
AE1
AE25
B4
C1
C10
C4
C6
D3
D6
D8
E5
E6
E7
F5
F6
F7
F8
G10
G19
G3
H12
H15
H18
H8
J12
J15
J18
J2
J8
K10
K12
K15
K18
K8
L10
L12
L15
L18
L2
L5
L8
M10
M12
M15
M18
M8
N10
N15
N18
N8
P10
P12
P15
P18
P8
R12
R15
R17
R8
T11
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_23
C61C
1
2
GND_29
+GND
G9
1.2V
C24C
2
1
1
A13
C71C
A25
0.22uF, 6.3V, X5R 10%
VDD_SNVS_CAP
VDD_SNVS_IN
C62C
+GND
2
G11
3.0V
2
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
2
10uF, 10V, X5R, 20%
H10
J10
C23C
supplied by internal regulator
C56C
C57C
C58C
C59C
1
1.2V
+GND
VDDHIGH_CAP_1
VDDHIGH_CAP_2
C22C
GND_21
1
N12
C12C
+GND
2
VDD_CACHE_CAP
1.2V
C10C
supplied by internal regulator
C38C
C39C
C40C
C41C
2
H17
J17
K17
L17
M17
N17
P17
1.2V
C11C
0.22uF, 6.3V, X5R 10%
1
2
2
1
2
2
A
K
2
GND_18
VDDPU_CAP_1
VDDPU_CAP_2
VDDPU_CAP_3
VDDPU_CAP_4
VDDPU_CAP_5
VDDPU_CAP_6
VDDPU_CAP_7
C27C
0.22uF, 6.3V, X5R 10%
C67C
+3V
VDDHIGH_IN_1
VDDHIGH_IN_2
R10
T10
T13
T14
U10
U13
U14
supplied by internal regulator
0.22uF, 6.3V, X5R 10%
10uF, 10V, X5R, 20%
0.22uF, 6.3V, X5R 10%
1
0.22uF, 6.3V, X5R 10%
1
0.22uF, 6.3V, X5R 10%
H9
J9
3.0V
1
0.22uF, 6.3V, X5R 10%
P3.0V_VDDHIGH_SW2
2
D
D10C
RB751V40,115
0.22uF, 6.3V, X5R 10%
+3V
47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
P3.0V_STBY
C68C
SW2
VDDSOC_CAP_1
VDDSOC_CAP_2
VDDSOC_CAP_3
VDDSOC_CAP_4
VDDSOC_CAP_5
VDDSOC_CAP_6
VDDSOC_CAP_7
C21C
GND_19
1
1
2
2
GND_17
+GND
C
H16 VDDSOC_IN_1
J16 VDDSOC_IN_2
K16 VDDSOC_IN_3
22uF, 6.3V, X5R,
L1620%VDDSOC_IN_4
M16 VDDSOC_IN_5
N16 VDDSOC_IN_6
P16 VDDSOC_IN_7
R16 VDDSOC_IN_8
T16 VDDSOC_IN_9
U16 VDDSOC_IN_10
C51C
1
1
1
2
2
2
C50C
2
1
1
C49C
2
1
1
C48C
2
1
2
2
1
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
C47C
1
C46C
1
C45C
C52C
2
1
2
1
2
2
2
2
1
1
C44C
1
C43C
1
+VDD
2
VDD_SOC_IN_SW1C
2
1.375V (power-on), 1.225V (nominal)
SW1C
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
i.MX6 D: short
H11
J11
K11
L11
M11
N11
P11
R11
C20C
+GND
1
+GND
VDDARM_CAP23_1
VDDARM_CAP23_2
VDDARM_CAP23_3
VDDARM_CAP23_4
VDDARM_CAP23_5
VDDARM_CAP23_6
VDDARM_CAP23_7
VDDARM_CAP23_8
VDD_ARM_CAP
C19C
2
GND_16
22uF, 6.3V, X5R, 20%
VDDARM23_IN_1
VDDARM23_IN_2
VDDARM23_IN_3
VDDARM23_IN_4
VDDARM23_IN_5
VDDARM23_IN_6
VDDARM23_IN_7
VDDARM23_IN_8
H13
J13
K13
L13
M13
N13
P13
R13
2
1
1
2
2
1
C34C
1
2
2
C33C
2
10uF, 10V, X5R, 20%
1
1
C32C
2
0.22uF, 6.3V, X5R 10%
1
1
2
2
0.22uF, 6.3V, X5R 10%
C31C
K9
L9
M9
N9
P9
R9
T9
U9
VDDARM_CAP_1
VDDARM_CAP_2
VDDARM_CAP_3
VDDARM_CAP_4
VDDARM_CAP_5
VDDARM_CAP_6
VDDARM_CAP_7
VDDARM_CAP_8
1
22uF, 6.3V, X5R, 20%
i.MX6Q - POWER
VDDARM_IN_1
VDDARM_IN_2
VDDARM_IN_3
VDDARM_IN_4
VDDARM_IN_5
VDDARM_IN_6
VDDARM_IN_7
VDDARM_IN_8
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
0.22uF, 6.3V, X5R 10%
C30C
2
i.MX6 Q,DL,S: open
2
2
2
2
2
2
1
GND_30
+GND
C18C
1
0.22uF, 6.3V, X5R 10%
1
1
1
2
B
C93C
2
1
2
1
1
2
1
1
1
C92C
2
1
C91C
C17C
GND_15
i.MX6 D: open
C90C
C16C
+GND
i.MX6 Q,DL,S: short
C89C
C15C
2
2
no support for i.MX6D - launch SKUs are Q and DL
C14C
2
H14
J14
K14
L14
M14
N14
P14
R14
+1.2V
0.22uF, 6.3V, X5R 10%
0.22uF, 6.3V, X5R 10%
VCC_1.2V_SW1AB
C13C
A
U100
iMX6Q - MCIMX6Q5EYM12AC
1.375V (power-on), 1.35V (nominal)
SW1A/B
0.22uF, 6.3V, X5R 10%
J10C
1
test point (DNP)
J11C
T12
T15
T17
T19
T8
U11
U12
U15
U17
U8
U19
V8
V19
W3
W7
W8
W9
W10
W11
W12
W13
W15
W16
W17
W18
W19
Y5
Y24
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_13
1
1
1
test point (DNP)
J12C
1
G
1
test point (DNP)
H
Copyright 2014 Andrew "bunnie" Huang
GND_14
+GND
+GND
Sheet: /U_02cpu_power/
File: 02cpu_power.sch
Novena PVT2-A
Title: 02cpu_power
Copyrights: CC-BY-SA 3.0
1
2
3
4
5
6
7
8
Size: C
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
Patents: Apache 2.0
9
10
Rev:
Id: 2/16
11
1
2
3
4
5
1
1
2
GND_46
+GND
Copyrights:
CC-BY-SA 3.0
2
Patents: Apache
2.0
3
1
2
2
DDR3_DQS7_N
DIFFPAIR
DDR3_DQS7_PDIFFPAIR
P3.3V_DELAYED_7
1
+3.3V
R12M
10k, 1%
2
2
1
DDR3_D62
DDR3_D63
1
1
2
2
1
C36M
2
1
C50M
C51M
C38M
C52M
GND_41
+GND
GND_42
+GND
1
G
C53M
H
Novena PVT2-A
Title: 03cpu_sodimm
Rev:
Id: 3/16
5
C20M
C39M
Copyright 2014 Andrew "bunnie" Huang
Size: B
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
2
1
C19M
2
1
+0.75V
1
P0.75V_DDR3_VTT
C18M
C37M
0.01uF, 10V, X5R, 10%
DDR3_EVENT_N
SMB_SDA
SMB_SCL
Sheet: /U_03cpu_sodimm/
File: 03cpu_sodimm.sch
4
1
0.22uF, 6.3V, X5R 10%
1
1
DDR3_D60
DDR3_D61
2
2
1
C49M
2
F
DDR3_D54
DDR3_D55
0.01uF, 10V, X5R, 10%
0.22uF, 6.3V, X5R 10%
1
1
2
2
1
C35M
2
1
2
2
1
2
2
1
C48M
0.01uF, 10V, X5R, 10%
0.22uF, 6.3V, X5R 10%
1
0.01uF, 10V, X5R, 10%
0.22uF, 6.3V, X5R 10%
1
1
2
2
C34M
1
C47M
1
1
C46M
2
1
0.01uF, 10V, X5R, 10%
0.22uF, 6.3V, X5R 10%
1
1
2
2
1
2
2
1
C45M
C33M
2
DDR3_DM6
GND_32
C32M
0.01uF, 10V, X5R, 10%
DDR3_D52
DDR3_D53
2
1
DDR3_D46
DDR3_D47
DDR3 SODIMM socket, reverse pinout
+GND
GND_31
0.01uF, 10V, X5R, 10%
0.22uF, 6.3V, X5R 10%
1
2
1
C44M
2
1
1
2
2
1
1
2
C43M
47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
P5.0V
2
1
2
1
2
2
2
1
+5V
1
RT9045GSP
1
2
47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
C56M
R13M
2
2.2 ohm, 5%
C54M
1.0uF, 25V, 20% X5R
2
2
1
R14M
C42M
47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
1
10uF, 10V, X5R, 20%
2
2
1
+GND
1
VTT_VCNTL
GND_45
1.0uF, 25V, 20% X5R
6
2
1
1k, 1%
1
1
1
C55M
VIN
GND
REFEN
VOUT
1
1.0uF, 25V, 20% X5R
VCNTL
U10M
1
2
3
4
2
2
R16M
0 ohm, 0805 (DNP)
C41M
C17M
+GND
+1.5V
1
1
2
9
1
1
2
2
1
R15M
+0.75V
1
GND
C40M
+1.8V
P0.75V_DDR3_VTT_2
2
0 ohm, 0805
+1.5V
P1.8V_SW4
2
10uF, 10V, X5R, 20%
H
P1.5V_DDR_SW3_5
GND_47
+GND
2
0.1uF, 6.3V, X5R
+0.75V
GND_43
+GND
DDR3_DQS5_N
DIFFPAIR
DDR3_DQS5_PDIFFPAIR
P1.5V_DDR_SW3_2
Option: SW4 power supply instead of SW3 to reduce VTT power:
SW4 is unused, so reprogram in BSP to 1.1V
(Approx 0.3-0.4V min drop-out @ 0.5A, 100C))
P0.75V_REFDDR_4
+3.3V
1
0.22uF, 6.3V, X5R 10%
1
2
1
C31M
2
2
1
C30M
2
2
1
C29M
2
0.22uF, 6.3V, X5R 10%
1
0.22uF, 6.3V, X5R 10%
1
0.22uF, 6.3V, X5R 10%
1
1
2
2
0.22uF, 6.3V, X5R 10%
1
1
2
2
1
2
2
22uF, 6.3V, X5R, 20%
1
1
1
2
C28M
GND_44
+GND
P3.3V_DELAYED_8
2
+1.5V
2
P1.5V_DDR_SW3
E
DDR3_D44
DDR3_D45
2
DDR3_D58
DDR3_D59
C15M
1
DDR3_DM7
DDR3_D38
DDR3_D39
1
DDR3_D56
DDR3_D57
DDR3_DM4
C14M
GND_37
+GND
2
DDR3_D50
DDR3_D51
+0.75V
DDR3_D36
DDR3_D37
2
DIFFPAIR DDR3_DQS6_N
DIFFPAIR DDR3_DQS6_P
P0.75V_REFDDR_2
1
GND_40
2
R18
T18
U18
V10
V11
V12
V13
V14
V15
V16
V17
V18
V9
D
1
DDR3_D48
DDR3_D49
R11M
240, 1%
+GND
+1.5V
2
DDR3_D42
DDR3_D43
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
VDD
VREFCA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5_N
DQS5_P
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7_N
DQS7_P
VSS
DQ62
DQ63
VSS
EVENT_N
SDA
SCL
VTT
P1.5V_DDR_SW3_4
2
+GND
C16M
2
ZQPAD AE17 DDR3_ZQPAD
DDR3_DM5
GND_35
1
+0.75V
1
P0.75V_REFDDR_3
2
AC2
GND_34
0.22uF, 6.3V, X5R 10%
DDR3_D40
DDR3_D41
C27M
VSS
DQ32
DQ33
VSS
DQS4_N
DQS4_P
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6_N
DQS6_P
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
C
DDR3_D30
DDR3_D31+GND
0.01uF, 10V, X5R, 10%
0.22uF, 6.3V, X5R 10%
DDR3_D32
DDR3_D33
DDR3_D34
DDR3_D35
C26M
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR3_DQS3_N
DIFFPAIR
DDR3_DQS3_PDIFFPAIR
1
1
1
2
DDR_CLK1
DIFFPAIR DDR3_DQS4_N
DIFFPAIR DDR3_DQS4_P
0.01uF, 10V, X5R, 10%
2
DDR3_A13
DDR3_CS1
C13M
DDR3_D28
DDR3_D29
1
DDR_CLK1
DDR3_D22
DDR3_D23
2
1
1
2
2
DDR3_WE
DDR3_CAS
DIFFPAIR
DRAM_SDCLK_1 AD14 DDR3_CK1_P
DIFFPAIR
DRAM_SDCLK_1_B AE14 DDR3_CK1_N
C25M
2
1
2
0.01uF, 10V, X5R, 10%
1
0.01uF, 10V, X5R, 10%
1
1
2
C24M
GND_38
+GND
DDR3_A10
DDR3_BA0
C12M
DDR_CLK0
DDR3_DM2
2
DDR_CLK0
DDR3_D20
DDR3_D21
1
DIFFPAIR
DRAM_SDCLK_0 AD15 DDR3_CK0_P
DIFFPAIR
DRAM_SDCLK_0_B AE15 DDR3_CK0_N
DDR3_CK0_P
DDR3_CK0_N
B
DDR3_D14
DDR3_D15
1
DDR3_A3
DDR3_A1
10k, 1%
DDR3_DM1
DDR3_RESET
2
GND_39
+GND
2
2
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1_P
CK1_N
VDD
BA1
RAS_N
VDD
S0_N
ODT0
VDD
ODT1
DDR3_D12
DDR3_D13
2
DDR3_A8
DDR3_A5
DDR3_RESET
DDR_CTL
1
DRAM_D56
DRAM_D57
DRAM_D58
DRAM_D59
DRAM_D60
DRAM_D61
DRAM_D62
DRAM_D63
DRAM_SDQS7
DRAM_SDQS7_B
DRAM_DQM7
C23M
2
1
2
2
0.22uF, 6.3V, X5R 10%
1
0.22uF, 6.3V, X5R 10%
1
1
2
2
0.22uF, 6.3V, X5R 10%
C22M
1
2
DDR3_BA2
DDR3_A12
DDR3_A9
R10M
NVCC_DRAM_1
NVCC_DRAM_2
NVCC_DRAM_3
NVCC_DRAM_4
NVCC_DRAM_5
NVCC_DRAM_6
NVCC_DRAM_7
NVCC_DRAM_8
NVCC_DRAM_9
NVCC_DRAM_10
NVCC_DRAM_11
NVCC_DRAM_12
NVCC_DRAM_13
BA2
VDD
A12
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0_P
CK0_N
VDD
A10
BA0
VDD
WE_N
CAS_N
VDD
A13
S1_N
VDD
+1.5V
1
DRAM_VREF
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
74 DDR3_CKE1
76
78
DDR3_A15
80
DDR3_A14
82
84
DDR3_A11
86
DDR3_A7
88
90
DDR3_A6
92
DDR3_A4
94
96
DDR3_A2
98
DDR3_A0
100
102
DDR3_CK1_P
104
DDR3_CK1_N
106
108
DDR3_BA1
110
DDR3_RAS
112
114
DDR3_CS0
116
DDR3_ODT0
118
120
DDR3_ODT1
2
Y6
DRAM_RESET
CKE0
VDD
DDR3_D6
DDR3_D7
1
DDR3_ODT0
DDR_CTL
DDR3_ODT1
DDR_CTL
73
75
DDR3_DQS0_N
DIFFPAIR
DDR3_DQS0_PDIFFPAIR
1
DRAM_SDODT0 AC16
DRAM_SDODT1 AB17
DDR3_CKE0
P1.5V_DDR_SW3_3
DDR3_D4
DDR3_D5
2
DDR3_CKE0
DDR_CTL
DDR3_CKE1
DDR_CTL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
DRAM_SDCKE0 Y11
DRAM_SDCKE1 AA11
DDR3_D26
DDR3_D27
+GND
GND_33
VREFDQ
VSS
VSS
DQ4
DQ0
DQ5
DQ1
VSS
VSS
DQS0_N
DM0
DQS0_P
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1_N
DM1
DQS1_P RESET_N
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2_N
DM2
DQS2_P
VSS
VSS
DQ22
DQ18
DQ23
DQ19
VSS
VSS
DQ28
DQ24
DQ29
DQ25
VSS
VSS
DQS3_N
DM3
DQS3_P
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
0.01uF, 10V, X5R, 10%
0.22uF, 6.3V, X5R 10%
DDR3_RAS
DDR_CTL
DDR3_CAS
DDR_CTL
DDR3_WEDDR_CTL
G
C21M
2
1
1
DRAM_RAS AB15
DRAM_CAS AE16
DRAM_SDWE AB16
address 0xA0
DDR_D7DDR3_D56 AB25
DDR_D7DDR3_D57 AA21
DDR_D7DDR3_D58 Y25
DDR_D7DDR3_D61 Y22
DDR_D7DDR3_D60 AB23
DDR_D7DDR3_D59 AA23
DDR_D7DDR3_D63 Y23
DDR_D7DDR3_D62 W25
DDR3_DQS7_PAA25
DDR3_DQS7_NAA24
DDR_D7DDR3_DM7 Y21
2
DDR3_DM3
2
DRAM_D48
DRAM_D49
DRAM_D50
DRAM_D51
DRAM_D52
DRAM_D53
DRAM_D54
DRAM_D55
DRAM_SDQS6
DRAM_SDQS6_B
DRAM_DQM6
DDR3_D24
DDR3_D25
2.2pF, NP0 (DNP)
DDR_D6DDR3_D48 AC22
DDR_D6DDR3_D54 AE22
DDR_D6DDR3_D50 AE24
DDR_D6DDR3_D52 AC24
DDR_D6DDR3_D53 AB22
DDR_D6DDR3_D51 AC23
DDR_D6DDR3_D49 AD25
DDR_D6DDR3_D55 AC25
DDR3_DQS6_PAD23
DDR3_DQS6_NAE23
F
DDR_D6
DDR3_DM6 AD24
DDR3_CS0
DDR_CTL
DDR3_CS1
DDR_CTL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
DRAM_CS0 Y16
DRAM_CS1 AD17
2.2pF, NP0 (DNP)
DRAM_D40
DRAM_D41
DRAM_D42
DRAM_D43
DRAM_D44
DRAM_D45
DRAM_D46
DRAM_D47
DRAM_SDQS5
DRAM_SDQS5_B
DRAM_DQM5
DIFFPAIR DDR3_DQS2_N
DIFFPAIR DDR3_DQS2_P
1
DDR_D5DDR3_D40 Y19
DDR_D5DDR3_D41 AB20
DDR_D5DDR3_D42 AB21
DDR_D5DDR3_D44 AD21
E
DDR_D5
DDR3_D45 Y20
DDR_D5DDR3_D43 AA20
DDR_D5DDR3_D47 AE21
DDR_D5DDR3_D46 AC21
DDR3_DQS5_PAD20
DDR3_DQS5_NAE20
DDR_D5DDR3_DM5 AC20
DDR3_D16
DDR3_D17
1
DRAM_D32
DRAM_D33
DRAM_D34
DRAM_D35
DRAM_D36
DRAM_D37
DRAM_D38
DRAM_D39
DRAM_SDQS4
DRAM_SDQS4_B
DRAM_DQM4
DDR3_D10
DDR3_D11
DDR3_D18
DDR3_D19
DRAM_D24
DRAM_D25
DRAM_D26
DRAM_D27
DRAM_D28
DRAM_D29
DRAM_D30
DRAM_D31
DRAM_SDQS3
DRAM_SDQS3_B
DRAM_DQM3
DDR_D4DDR3_D32 AA17
DDR_D4DDR3_D38 AA18
DDR_D4DDR3_D39 AC18
DDR_D4DDR3_D33 AE19
DDR_D4DDR3_D36 Y17
DDR_D4DDR3_D34 Y18
DDR_D4DDR3_D37 AB19
DDR_D4DDR3_D35 AC19
DDR3_DQS4_PAD18
DDR3_DQS4_NAE18
DDR_D4DDR3_DM4 AB18
DIFFPAIR DDR3_DQS1_N
DIFFPAIR DDR3_DQS1_P
1
DDR_D3DDR3_D24 AE9
DDR_D3DDR3_D27 Y10
DDR_D3DDR3_D25 AE11
DDR_D3DDR3_D26 AB11
DDR_D3DDR3_D31 AC9
DDR_D3DDR3_D29 AD9
DDR_D3DDR3_D28 AD11
DDR_D3DDR3_D30 AC11
DDR3_DQS3_PAC10
DDR3_DQS3_NAB10
D
DDR_D3
DDR3_DM3 AE10
DDR3_D8
DDR3_D9
1
DRAM_D16
DRAM_D17
DRAM_D18
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D22
DRAM_D23
DRAM_SDQS2
DRAM_SDQS2_B
DRAM_DQM2
DDR3_BA0
DDR_CTL
DDR3_BA1
DDR_CTL
DDR3_BA2
DDR_CTL
DDR3_DM0
DDR3_D2
DDR3_D3
2
DDR_D2DDR3_D16 AB7
DDR_D2DDR3_D22 AA8
DDR_D2DDR3_D19 AB9
DDR_D2DDR3_D21
Y9
DDR_D2
DDR3_D18
Y7
C
DDR_D2DDR3_D23
Y8
DDR_D2DDR3_D17 AC8
DDR_D2DDR3_D20 AA9
DDR3_DQS2_P AD8
DDR3_DQS2_N AE8
DDR_D2DDR3_DM2 AB8
DRAM_SDBA0 AC15
DRAM_SDBA1 Y15
DRAM_SDBA2 AB12
+0.75V
2
DRAM_D8
DRAM_D9
DRAM_D10
DRAM_D11
DRAM_D12
DRAM_D13
DRAM_D14
DRAM_D15
DRAM_SDQS1
DRAM_SDQS1_B
DRAM_DQM1
DDR3_A0DDR_CTL
DDR3_A1DDR_CTL
DDR3_A2DDR_CTL
DDR3_A3DDR_CTL
DDR3_A4DDR_CTL
DDR3_A5DDR_CTL
DDR3_A6DDR_CTL
DDR3_A7DDR_CTL
DDR3_A8DDR_CTL
DDR3_A9DDR_CTL
DDR3_A10
DDR_CTL
DDR3_A11
DDR_CTL
DDR3_A12
DDR_CTL
DDR3_A13
DDR_CTL
DDR3_A14
DDR_CTL
DDR3_A15
DDR_CTL
0.1uF, 6.3V, X5R
DDR_D1DDR3_D8
AD5
DDR_D1DDR3_D12 AE5
DDR_D1DDR3_D13 AA6
DDR_D1DDR3_D14 AE7
DDR_D1DDR3_D11 AB5
DDR_D1DDR3_D15 AC5
DDR_D1DDR3_D9
AB6
DDR_D1DDR3_D10 AC7
DDR3_DQS1_P AD6
DDR3_DQS1_N AE6
DDR_D1DDR3_DM1 AC6
AC14
AB14
AA14
Y14
W14
AE13
AC13
Y13
AB13
AE12
AA15
AC12
AD12
AC17
AA12
Y12
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A15
JP10M
P0.75V_REFDDR
2
DRAM_D0
DRAM_D1
DRAM_D2
DRAM_D3
DRAM_D4
DRAM_D5
DRAM_D6
DRAM_D7
DRAM_SDQS0
DRAM_SDQS0_B
DRAM_DQM0
C11M
DDR3_D0
DDR3_D1
2
DDR_D0DDR3_D0
AD2
DDR_D0DDR3_D1
AE2
DDR_D0DDR3_D2
AC4
DDR_D0DDR3_D6
AA5
DDR_D0DDR3_D4
AC1
DDR_D0DDR3_D5
AD1
DDR_D0DDR3_D3
AB4
DDR_D0DDR3_D7
AE4
DDR3_DQS0_P AE3
DDR3_DQS0_N AD3
DDR_D0
DDR3_DM0 AC3
B
GND_36
+GND
0.01uF, 10V, X5R, 10%
0.22uF, 6.3V, X5R 10%
i.MX6Q - DDR
C10M
2
U100_2
iMX6Q - MCIMX6Q5EYM12AC
0.22uF, 6.3V, X5R 10%
A
0.01uF, 10V, X5R, 10%
A
1
2
3
4
5
6
7
8
POR default = 1.8V
4.7uF, 10V, X5R, 10%
P1.8V_VGEN4_2
POR default = 2.5V
1
+1.8V
POR default = 2.8V
A
+1.8V
1
C13P
GND_56
2
+GND
1
D10P
power LED
A
C16P
K
GND_58
2
1
+2.8V
+GND
2
APT1608EC red
2
C15P
2
2
GND_57
+GND
P2.8V_VGEN6
1
1
1
+2.5V
2
P2.5V_VGEN5_4
2
4.7uF, 10V, X5R, 10%
4.7uF, 10V, X5R, 10%
1
1
2
2
P1.8V_VGEN4
2
4.7uF, 10V, X5R, 10%
1
1
2
2
4.7uF, 10V, X5R, 10%
1
1
2
2
C12P
GND_55
+GND
R10P
49.9, 1%
1
1
R20P
1
2
1
1
1
1
2
C22P
B
BT10P
ML-621S/DN (DNP)
2
-
P3.3V_9
+3.3V
2
2
C24P
2
+GND
GND_59
+GND
1
1
1
+3V
GND_60
R19P
1k, 1% (DNP)
+
P3.0V_STBY_2
P3.3V_8
1k, 1% (DNP)
2
0.1uF, 6.3V, X5R
2
C23P
2
+3.3V
2
POR default = 3.0V
2
1
+3.3V
0.1uF, 6.3V, X5R
1
1
2
2
+1.8V
P3.3V_LICELL
1
1
2
GND_52
+GND
1
1
1
OSC1
OSC2
2
1
+
-
BT11P
BR1225A/FAN
GND_83
+GND
2
GND_73
+GND
C47P
U200_3
INTB
1
47
55
VDDOTP
VDDIO
54
53
SCL
SDA
ICTEST
5
1.0uF, 25V, 20% X5R
2
1
DDC_SCL
DDC_SDA
+3.3V
4
2
1
2
1
R17P
0 ohm (DNP)
2
R18P
0 ohm
E
1
2
1
1
1
+GND
C52P
C60P
0.1uF, 6.3V, X5R
1
2
+GND
GND_82
C53P
+GND
GND_76
2
2
2
10uF, 10V, X5R, 20% (DNP)
1
1
1
10uF, 10V, X5R, 20% (DNP)
1
GND_77
test point (DNP)
3
PMIC_INT_B
P3.3V_7
1
J10P
1
PMIC_SDWNB
2
R16P
0 ohm (DNP)
2
2
2
VDDOTP
1
2
SDWNB
P3.3V_DELAYED_10
68k, 1% +3.3V
R14P
68k, 1%
1
1
Copyrights:
CC-BY-SA 3.0
5
D
P3.0V_STBY_4
+3V
RESETBMCU
PMIC_STBY_REQ R13P
1
1
2
VCORE
GNDREF
2
48
0.1uF, 6.3V, X5R49
1
2
2
1k, 1%
C51P
2
10k, 1%
56
3
4
PMIC_ON_REQ
2
1
2
2
1
1
VIN
PWRON
VCOREDIG RESETBMCU
VCOREREF
STANDBY
R12P
1
2
50
51
52
P3.3V_6
+3.3V
C50P
2
R15P
PMIC_PWRON
1
1
C46P
2
1
1
+1.5V
GND_74
+GND
2
1.0uF, 25V, 20% X5R
VCOREDIG
2
1
R11P
10k, 1%
1
1
2
2
+3V
MMPF0100NPAEP
2
C
Device address = 0xD0/0xD1
P3.0V_STBY_3
C49P
+8V on J10P to program OTP
Remove R15P, populate R17P, C52P, C53P to program
Remove R15P, R17P, populate R16P, C52P, C53P to boot from fuses
SMB_SCL
SMB_SDA
PCF8523T/1
C42P
GND_75
E
8
7
6
5
2
1
2
1
C39P
2
1
2
2
1
2
2
22uF, 6.3V, X5R, 20%
1
22uF, 6.3V, X5R, 20%
1
22uF, 6.3V, X5R, 20%
1
2
2
C38P
1
GND_71
+GND
+1.5V
Y10P
4.7uF, 10V, X5R, 10%
OSCI
VDD
OSCO INT1/CLK
VBAT
SCL
VSS
SDA
1
1
2
GND_70
+GND
1
C48P
1
GND_72
+GND
+5V
2
2
C59P
P5.0V_SWBST
Must configure CL = 12.5pF via I2C!
Abracon ABS06-32.768KHZ-T 12.5pF CL
1
1
2
2
0.1uF, 6.3V, X5R
1
2
2
1
22uF, 6.3V, X5R, 20%
1
2
2
+1.8V
2
GND_81
+GND
P3.3V_5
+3.3V
P1.5V_DDR_SW3_8
U10P
1
2
3
4
2
P1.8V_SW4_2
2
D11P
MBR140SFT
C37P
2
A
L15P
C36P
GND_68
+GND
1.0uF, 25V, 20% X5R
+5V
K
1
P5.0V_SWBST_2
22uF, 6.3V, X5R, 20%
2
1
1
46
45
44
1
0.1uF, 6.3V, X5R
1
4.7uF, 10V, X5R, 10%
1
1
2
2
1
1
2
4.7uF, 10V, X5R, 10%
4.7uF, 10V, X5R, 10%
2
2
1
C57P
POR default = 1.5V
POR default = 1.8V
1
10uF, 10V, X5R, 20%
GND_66
+GND
2
GND_84
+GND
2
1
2
C58P
2
1
C31P
C61P
+GND
1
R21P
1k, 1%
1
2
GND_80
+GND
2
2
C45P
1
1uH LPS4018-102
SWBSTLX
SWBSTIN
SWBSTFB
C30P
L10P
L13P
2.2uH LPS4018-222
SW2FB
C29P
GND_69
1
25
MMPF0100NPAEP
1
1
1
2
GND_65
+GND
+3V
1
P3.3V_3
+3.3V
P3.0V_VDDHIGH_SW2_3
2
2
0.1uF, 6.3V, X5R
1uH LPS4018-102
+GND
C28P
+GND
1
SW2LX
SW2IN_1
SW2IN_2
19
20
21
P3.3V_4
+3.3V
GND_67
1uH LPS4018-102
2
22
23
24
SW4FB
SW4IN
SW4LX
+1.5V
2
SW1VSSSNS
32
P1.5V_DDR_SW3_7
10uF, 10V, X5R, 20%
14
SW3VSSSSNS
1
SW1CLX
SW1CIN
SW1CFB
38
37
36
35
34
33
1
11
12
13
SW3AFB
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
2
SW1FB
SW1AIN
SW1ALX
SW1BLX
SW1BIN
0.1uF, 6.3V, X5R
2
1
1
42
43
C11P
GND_54
+GND
P1.8V_VGEN3
GND_78
MMPF0100NPAEP
GNDREF1
6
7
8
9
10
EPGND
POR default = 3.0V
2
1
2
VHALF
LICELL
VSNVS
+1.5V
+GND
2
1
1
2
2
2
1uH LPS4018-102
4.7uF, 10V, X5R, 10%
22uF, 6.3V, X5R, 20%
1
1
2
VINREFDDR
29
U200_2
1
2
2
C20P
+1.2V
1
1
2
30
+1.5V
VCC_1.2V_SW1AB_2
1
C44P
P1.5V_DDR_SW3_6
C27P
GND_61
+GND
L11P
1
C43P
0.1uF, 6.3V,0.1uF,
X5R 6.3V, X5R
1
1
2
C19P
2
2
2
1
C26P
+VDD
GND_64
VREFDDR
+0.75V
GND_51
+GND
15
2
4.7uF, 10V, X5R, 10%
1
C35P
2
1
4.7uF, 10V, X5R, 10%
1
1
2
2
1
C25P
L14P
+GND
1
P0.75V_REFDDR_5
2
1.0uF, 25V, 20% X5R
C18P
16
18
26
28
39
41
P3.3V_2
VDD_SOC_IN_SW1C_3
+3V
31
1
1
2
GND_49
+GND
VGEN1
VGEN2
VGEN3
VGEN4
VGEN5
VGEN6
+3.3V
2
P3.0V_VDDHIGH_SW2_4
VIN1
VIN2
VIN3
+3.3V
2
0.1uF, 6.3V, X5R
P3.3V
17
27
40
C10P
GND_53
+GND
P1.5V_VGEN2
+GND
1uH LPS4018-102
C41P
1
C17P
2
1
2
1
1
2
GND_50
57
L12P
U200
+1.2V
2
4.7uF, 10V, X5R, 10%
1
2
2
22uF, 6.3V, X5R, 20%
1
1
2
2
1
2
2
1
0.1uF, 6.3V, X5R
1
1
22uF, 6.3V, X5R, 20%
2
2
0.1uF, 6.3V, X5R
1
1
1
22uF, 6.3V, X5R, 20%
1
1
2
2
D
C34P
+GND
GND_62
C14P
P1.2V_VGEN1
for low-voltage eMMC
GND_79
C56P
1
C40P
GND_63
+GND
C55P
C33P
22uF, 6.3V, X5R, 20%
+VDD
1
VDD_SOC_IN_SW1C_2
1
POR default = 1.375V
2
C
C32P
2
+1.2V
22uF, 6.3V, X5R, 20%
VCC_1.2V_SW1AB_3
22uF, 6.3V, X5R, 20%
22uF, 6.3V, X5R, 20%
2
2
0.1uF, 6.3V, X5R
C54P
GND_48
+GND
+3.3V
+GND
B
POR default = 1.375V
+3V
2
0.1uF, 6.3V, X5R
P3.3V_DELAYED_9
P3.0V_VDDHIGH_SW2_2
2
0.1uF, 6.3V, X5R
A
4.7uF, 10V, X5R, 10%
POR default = 1.5V
Copyright 2014 Andrew "bunnie" Huang
Sheet: /U_04pwr_pmic/
File: 04pwr_pmic.sch
Novena PVT2-A
Title: 04pwr_pmic
Patents: Apache
2.0
6
Size: B
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
7
Rev:
Id: 4/16
8
1
2
3
4
5
6
7
8
GND_96
+GND
C
1
1
M2 mounting
+GND hole
2
330, 1%
R26N
1
2
1
2
1
2
330, 1%
R27N
1
2
1
2
SMB_SCL
SMB_SDA
REG5V_FBK
1
1
2
2
1
1
2
2
22uF, 10V, X5R, 20% (DNP)
1
2
2
1
2
2
1
22uF, 10V, X5R, 20%
1
1
1
2
2
22uF, 10V, X5R, 20%
2
1
1
1
R25N
8.66k, 1%
+GND
UART4_TXD
UART4_RXD
C23N
P5.0V_DELAYED
GND_91
1
2
3
4
R24N
1
R23N
1
GND_90
+GND
Q10N
2
1
2
1
1
C22N
C25N
GND_93
2
1
2
330, 1%
22uF, 25V, X5R, 10% (DNP)
2
+GND
2
R21N
C21N
1
GND_89
GND_87
2
1
2
2
1
1
2
2
1
R15N
R16N
63.4k, 1% 4.99k, 1%
C20N
B
+5V
+GND
C26N
1
S
S
S
G
100k, 1%
P
+5V
D
D
D
D
8
7
6
5
Si4435DY
2
16
17
18
19
20
21
22
2
1
2
C24N
R20N
0 ohm (DNP)
+GND
330, 1%
1
1
1
1
1
1
+GND
2
NTMFS4C35NT1G
GND_92
2
9
8
7
6
5
5V @ 7A max
P5.0V_2
2
2
R19N
15k, 1%
D
D
D
D
D
330pF, X7R, 10%
1
1
set OC trip @ 15A
S
S
SN
G
1
2
2
0 ohm
2
BATT_NRST
2
1
2
2
2
1
0 ohm
R22N
2
2
3.3uH, MSS1260-332NL (DNP)
R12N
R13N
100, 1%
20 ohms, 1%
2
R17N
1
2
1
1
2
3
4
1
U12N
470pF, X7R, 10%
R14N
68k, 1%
R18N
1
2
1
1
2
2
REG5V_LSDR
1
1
2
2
2
2
1
C18N
330, 1%
1
1
1
2
2
1
2
10k, 1%
DNP
M2 mounting hole
M15N
CHG_PWRSWITCH
2
1
3.3uH, XAL7030-322MEC
L10N
2
1
1
2
2
1
1
GND
B+
BGND
AA+
GND
R39N
2
NCP3020B
C17N
place within MSS1260 pad
1
NTMFS4841NT1G
C16N
1
M2 mounting hole
M14N
C19N
L10NB
1
1
1
2
R11N
2
1
2
1
9
8
7
6
5
2
M2 mounting hole
M13N
1
D
D
D
D
D
1
1
8.06 ohm, 1%
R10N
REG5V_HSDR
REG5V_VSW
S
S
SN
G
C15N
1
1
6 to 12 cell NiMH
330pF, X7R, 10%
M2 mounting hole
M12N
1
2
3
4
C14N
GND_88
+GND
1
1
1
6-cell lead acid
1
1
U10N
BAT54T1G
GND_86
REG5V_COMP
1
M2 mounting hole
M11N
8
7
6
5
BST
HSDR
VSW
LSDR
A
C13N
+GND
4-cell Li-Ion (preferred)
2
B
1
3-cell Li-Ion (preferred)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
+12V
+12V
+12V
GND
OPT
GND
+5V
+5V
+5V
GND
GND
GND
+3.3V
+3.3V
+3.3V
8.2 pF, NP0
M10N
VCC
COMP
FB
GND
1
K
A
22uF, 10V, X5R, 20%
U11N
1
2
3
4
D12N
2
2
1
1
2
1
C12N
2-cell Li-Ion
J10N
0.1uF, 25V, X5R
1
1
2
C11N
GND_85
+GND
REG5V_BST
2
2
1
Compatible with:
Absolute max rating is 25V
+GND
2
6V-18V battery header
GND_95
R31N
2.2k, 1%
GND_110
1
1.0uF, 25V, 20% X5R
SSB44-E3/52T
+GND
2.5A typ max 3A peak @ 12V
22uF, 25V, X5R, 10%
2
1
1
C10N
A
7V-19V nominal range
GND_94
+GND
2
12V @ 3A
K
0.1uF, 25V, X5R
K
D11N
PESD24VL1BA
DC power + battery -> 5V regulator
BATT_PWR
2
A
2
2.1mm x 5.5mm DC jack
1
22uF, 25V, X5R, 10%
D10N
RAW_PWR
2
P
2
P
2
2
3
1
P
0.1uF, 25V, X5R
JP10N
A
Note: use R31N only in fixed installations. Remove if used with battery (rely on battery MCU to guarantee input cap discharge)
22uF, 25V, X5R, 10% (DNP)
Note: Do not use JP10N power plug when plugged into charger/battery board via J10N!!!
C
C27N
330, 1%
GND_98
1
2
1
MOLEX 87703-0001 male
2
P3.3V_DELAYED_12
R28N
GND_97
+GND
1.0uF, 25V, 20% X5R
R29N
10k, 1%
1
+3.3V
2
1
1
1
2
2
47k, 1%
2
R30N
2
1
1
3
2
1
D16N
G
+2.5V
S
D15N
K
D17N
K
D14N
K
K
K
P2.5V_VGEN5_5
D13N
D
1
1
1
1
1
47k, 1%
Q11N
2N7002W
2
GND_107
A
ESD5Z3.3T1
2
A
ESD5Z3.3T1
2
A
ESD5Z3.3T1
2
A
ESD5Z3.3T1
2
ESD5Z3.3T1
2
A
+GND
GND_99
+GND
2
RESET
1
FAN53541UCX
1
1
2
C29N
R35N
2
1
1
2
+3.3V
2
1
2
1
100k, 1%
C30N
1
S
S
S
G
1
C33N
P
APX803-44-SAG-7 or RT9818CXXGVL 4.2V-4.38V setpoint
+3.3V
D
D
D
D
8
7
6
5
GND_108
+GND
Reset monitor, PFUZE reset is too short
Si4435DY
2
1.0uF, 25V, 20% X5R
3.33V nom
E
R37N
31.6k, 1%
GND_104
+GND
R38N
10k, 1%
1
GND_102
+GND
P2.8V_VGEN6_2
S
G
Copyright 2014 Andrew "bunnie" Huang
Sheet: /U_05pwr_input/
File: 05pwr_input.sch
Q13N
2N7002W
Novena PVT2-A
Title: 05pwr_input
2
GND_106
+GND
2
+GND
2
1
+2.8V
1
GND_109
1
C4
C3
C2
C1
B3
B2
1
2
3
4
P3.3V_10
1
GND
GND
GND
GND
GND
GND
100k, 1%
+GND
Q12N
2
A3
A4
GND_100
3
2
FB
VOUT
1
C28N
10uF, 10V, X5R, 20% (DNP)
R36N
2
0.60uH, XAL4020-601ME
2
AGND
+GND
2
VCC
P3.3V_DELAYED_11
3
B4
2
1
2
C32N
GND_103
1
RESETBMCU
3.3V @ 5A max
D
+GND
D3
D4
E3
E4
22uF, 10V, X5R, 20%
VIN
VIN
VIN
VIN
1
1
GND_101
2
C31N
E2
E1
D2
D1
SW
SW
SW
SW
2
1
1
+5V
10nF, X7R, 50V 10%
P5.0V_3
2
E
2
22uF, 10V, X5R, 20%
1k, 1%
PGOOD
EN
MODE
2
1
A1
A2
B1
2
1
2
U13N
1
R34N
2
L11N
1
2
1
RESETBMCU
1
1
2
1k, 1%
2
2
R33N
1k, 1% (DNP)
1
+GND
GND
R32N
allow PFM
GND_105
1
2
+5V
U14N
+5V
2
5V -> 3.3V regulator
P5.0V_4
1
D
P5.0V_5
0.1uF, 25V, X5R
D
3
4
5
Copyrights:6 CC-BY-SA 3.0
Patents: Apache 2.0
Size: B
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
7
Rev:
Id: 5/16
8
1
2
3
4
5
6
7
8
A, B, and C correspond to labelled jumpers below
P3.3V_DELAYED_14
A
A
PMIC_STBY_REQ
PMIC_ON_REQ
10k, 1%
2
P_FUSE
Y10B
2
OSC2
1
OSC1
CLK1_N
CLK1_P
C7
D7
CLK2_N
CLK2_P
C5
D5
2
1
1
2
1
1
2
1
2
2
2
1
2
1
R34B
1
1
2
R57B
100, 1% (DNP)
DIFFPAIR
2
1
C12B
RTC_XTALI
RTC_XTALO
2
10M, 1% (DNP)
2
18pF, NP0
1
1
2
2
C11B
2
18pF, NP0
R33B
2
1
2.2M, 1%
1
10M, 1% (DNP)
C
DIFFPAIRPCIE_REFCLK_P
2
R32B
1
2
DIFFPAIRPCIE_REFCLK_N
XTALI
XTALO
DIFFPAIR
D9
C9
RTC_XTALO
RTC_XTALI
1
2
1
CLK2_N
CLK2_P
24.0000 MHz 15ppm 8pF 70 ohm ESR (NDK NX3225SA)
2 pin 1.27mm male header
Abracon ABS06-32.768KHZ-T 12.5pF CL
GND_114
Y11B
P3.3V_DELAYED_20
1
1
+3.3V
1
2
1
2
P_FUSE must be used alone, if at all
2
4.7k, 1%
2
4.7k, 1%
R44B
G
S
1
2
1
BT_CFG2_4
2
1
10k, 1%
1
1
BT_CFG2_3
2
1
BT_CFG2_4
<- replicate to isolate ->
BT_CFG1_6
3
D
1
Q11B
2N7002W
G
Q12B
2N7002W
header absent = boot from internal SD
header present = boot from external SD
+GND
BT_CFG1_1 = !BT_CFG2_3
BT_CFG2_4 = !BT_CFG2_3
2 pin 1.27mm male header
BT_CFG1_5
R42B
1
B
R45B
GND_121
2
BT_CFG1_6
G
S
1
R43B
4.7k, 1%
header absent = boot from SD
header present = boot from SATA
R56B BT_CFG1_6 = !BT_CFG1_5
Q13B
2N7002W
E
2
GND_120
1
Sheet: /U_06cpu_soc/
File: 06cpu_soc.sch
2
1
Copyright 2014 Andrew "bunnie" Huang
R55B
2
R54B
10k, 1%
1
1
2
2
R53B
10k, 1%
1
1
2
2
R52B
10k, 1%
2
2
1
10k, 1%
1
1
1
R51B
2
R50B
2
1
1
2
R49B
2
1
1
2
2
R48B
10k, 1%
1
1
2
2
1
2
R47B
10k, 1%
+GND
2
1
2
2
GND_119
10k, 1%
1
2
+GND
R46B
Novena PVT2-A
Title: 06cpu_soc
1
2
BOOT_CFG1[7:0]: 0XX0 00X0
BOOT_CFG2[7:0]: 001X X000
3
D
3
2
D
2
1
1
2
R39B
2
1
1
1
2
1
P_SATA
+3.3V
2
2
10k, 1%
BT_CFG1_5
2
1
BT_CFG1_1
1
1
+3.3V
4.7k, 1%
R40B
C
BT_CFG2_3
P3.3V_DELAYED_17
P3.3V_DELAYED_16
R38B
1
2
2 pin 1.27mm male header
4.7k, 1%
1
1
S
2
R41B
2
1
Boot select header precedence: P_USB (A) > P_SATA (B) > PEXT (C)
C14B
2
18pF, NP0
1
1
2
P_EXT
BT_CFG1_1
2
1
+3.3V
3
1
+3.3V
2
R37B
GND_115
2
18pF, NP0
EIM_DA0
EIM_DA1
EIM_DA2
EIM_DA3
EIM_DA4
EIM_DA5
EIM_DA6
EIM_DA7
EIM_DA8
EIM_DA9
EIM_DA10
EIM_DA11
EIM_DA12
EIM_DA13
EIM_DA14
EIM_DA15
C13B
+GND
P3.3V_DELAYED_18
1
Default boot: internal microSD
R36B
P3.3V_DELAYED_19
2
OSC1
2
OSC2
10k, 1%
2
1
+GND
1
1
+GND
CPU_XTALO
2
2
R26B
4.7k, 1%
GND_118
2
1
2
2
A7
B7
+GND
PCIE_CLK
2
2
1
1
D
S
CPU_XTALI
GND_116
1
F11
D11
1k, 1%
PMIC_STBY_REQ
PMIC_ON_REQ
R29B
header absent = boot from storage
header present = boot from USB
2
R35B
2
1
0 ohm (DNP)
1
+3.3V
1
1
1
4
TAMPER
R20B
PCIE_CLK
2
1
1
10k, 1%
3
2
2
1
1
1
100k, 1%
0 = disable tamper detect
TEST_MODE
E11
1
2
2
2
1
1
2
2
10k, 1% (DNP)
1
1
10k, 1%
E12
CPU_TAMPER
R19B
10k, 1%
2
note: SMB pins on this sheet are only used for D/Q config
P3.3V_DELAYED_13
1
NVCC_EIM2
CPU_TEST_MODE
R22B
10k, 1% (DNP)
10k, 1%
EIM_EB0
EIM_EB1
K21
K23
BOOT_MODE0
BOOT_MODE1
1
Q10B
2N7002W
R28B
1
16
+GND
+3.3V
D
EIM_BCLK
EIM_WAIT
2
C12
F12
2 pin 1.27mm male header
G
14
GND_117
P3.3V_DELAYED_15
2
N22
M25
2
1
A
+GND
12
Male 2.54mm 8x2 header (DNP)
2
EIM_BCLK
EIM_WAIT
R25B
CPU_BOOTMODE0
CPU_BOOTMODE1
H5
C3
G5
G6
C2
H6
2
DDC_SCL
P_USB
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRSTB
JTAG_MOD
1
E22
F23
GND_113
15
8
10
1
EIM_EB2
EIM_EB3
P3.3V_12
R27B
13
6
2
DDC_SDA
I2C3_SCL
I2C3_SDA
EPIT1_EPITO
EPIT2_EPITO
SMB_SCL
PCIE_WAKE
RGMII_NRST
UART3_TXD
UART3_RXD
UART2_TXD
UART2_RXD
SMB_SDA
PCIE_RST
SATA_PWRON
ONOFF
POR_B
2
C25
F21
D24
G21
G20
H20
E23
D25
F22
G22
E24
E25
G23
J19
J20
H21
D12
C11
1
EIM_D16
EIM_D17
EIM_D18
EIM_D19
EIM_D20
EIM_D21
EIM_D22
EIM_D23
EIM_D24
EIM_D25
EIM_D26
EIM_D27
EIM_D28
EIM_D29
EIM_D30
EIM_D31
CEC
1
1
11
4
1
H19
9
2
i.MX6Q - CONTROL
CPU_ONOFF
RESETBMCU
R23B
7
2
4
6
8
10
12
14
16
B
0.1uF, 25V, X5R (DNP)
+3.3V
5
1
3
5
7
9
11
13
15
0 ohm
1
EIM_A25
EIM_DA0
EIM_DA1
EIM_DA2
EIM_DA3
EIM_DA4
EIM_DA5
EIM_DA6
EIM_DA7
EIM_DA8
EIM_DA9
EIM_DA10
EIM_DA11
EIM_DA12
EIM_DA13
EIM_DA14
EIM_DA15
1
2
3
4
1
1
1
EIM_A16
EIM_A17
EIM_A18
UIM_DATA
UIM_CLK
UIM_RESET
PCIE_WDIS_N
UIM_PWRON
HDMI_HPD_CPU
2
2
H25
G24
J22
G25
H22
H23
F24
J21
F25
2
U100_3
iMX6Q - MCIMX6Q5EYM12AC
10k, 1%
EIM_A16
EIM_A17
EIM_A18
EIM_A19
EIM_A20
EIM_A21
EIM_A22
EIM_A23
EIM_A24
L20
J25
L21
K24
L22
L23
K25
L25
L24
M21
M22
M20
M24
M23
N23
N24
RESETBMCU R18B
NVCC_JTAG
EIM_CS0
EIM_CS1
10k, 1%
E
H24
J23
10k, 1%
NVCC_EIM1
NVCC_EIM0
D
1
1
+GND
C10B
EIM_CS0
EIM_CS1
R13B
100, 1%
P10B
3
JTAG_JTDO
JTAG_NRST
Heat sink Advanced Thermal Solutions ATS-56001-C3-R0
GND_111
+GND
2
C
NT10B
JTAG_JRST
JTAG_JTDI
JTAG_JTMS
JTAG_JTCK
JTAG_RTCK
GND_112
2
B
3
2
2
4
3
1
EIM_LBA
EIM_OE
EIM_RW
10k, 1%
K22
J24
K20
2
1
EIM_LBA
EIM_OE
EIM_RW
BT_CFG1_0
BT_CFG1_1
BT_CFG1_2
BT_CFG1_3
BT_CFG1_4
BT_CFG1_5
BT_CFG1_6
BT_CFG1_7
BT_CFG2_0
BT_CFG2_1
BT_CFG2_2
BT_CFG2_3
BT_CFG2_4
BT_CFG2_5
BT_CFG2_6
BT_CFG2_7
R17B
10k, 1%
2
1
2
3
4
+3.3V
i.MX6Q - EIM
R16B
10k, 1%
1
DNP; CPU power state controlled by charger board
P3.3V_11
R15B
10k, 1%
Male 2.54mm 2x1 right angle (DNP)
TL3342F160QG/TR (DNP)
SW11B
VDD_SNVS_IN
2
R14B
10k, 1%
TL3342F160QG/TR
SW10B
1
10k, 1%
1
2
U100_4
iMX6Q - MCIMX6Q5EYM12AC
2
hard reset
P_TAMPER
2
2
2
2
+3.3V
4
Copyrights:
CC-BY-SA 3.0
5
Patents: Apache
2.0
6
Size: B
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
7
Rev:
Id: 6/16
8
2
3
P3.3V_DELAYED_26
i.MX6Q
1
1
2
SD3_CMD
SD3_CLK
SD3_DAT0
SD3_DAT1
SD3_DAT2
SD3_DAT3
B13
D14
E14
F14
A15
B15
D13
C13
E13
F13
D15
SD3_CMD
SD3_CLK
SD3_DAT0
SD3_DAT1
SD3_DAT2
SD3_DAT3
SD3_DAT4
SD3_DAT5
SD3_DAT6
SD3_DAT7
SD3_RST
ensure low voltage for proper reset
SD3_RST_N
MLB_CP
MLB_CN
B9
A9
MLB_SP
MLB_SN
A10
B10
MLB_DP
MLB_DN
1
1
B11
A11
2
2
1
1
2
1
R18S
10k, 1%
R19S
10k, 1%
2
1
2
SD2_DAT0
SD2_DAT1
SD2_DAT2
SD2_WP
+GND
P3.3V_DELAYED_27
+3.3V
P3.3V_DELAYED_28
Device addr = 0xAC
NVCC_NANDF
E
U10S
1
1
+3.3V
2
GND_133
+GND
1
2
3
4
C14S
2
0.1uF, 6.3V, X5R
+3.3V
P3.3V_DELAYED_29
A0
A1
A2
GND
VCC
WP
SCL
SDA
8
7
6
5
I2C3_SCL
I2C3_SDA
GND_132
GND_134
+GND
+GND
FT24C512AUTR-T
Utility EEPROM, 64kx8
Store non-volatile configuration info
And possibly parts of panic logs
1
UART4_TXD
DQ only
UART4_RXD
KEY_COL1
KEY_ROW1
KEY_COL2
+3.3V
KEY_ROW2
R15S
KEY_COL3
10k, 1%
KEY_ROW3
KEY_COL4
LCD_BL_ON
Place mirror-image on bottom side of board
TL3342F160QG/TR (DNP)
SW11S
TL3342F160QG/TR
SW10S
B
1
2
3
4
P3.3V_DELAYED_30
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_16
GPIO_17
GPIO_18
GPIO_19
T5
T4
T1
R7
R6
R4
T3
R3
R5
T2
R2
R1
P6
P5
NANDF_CS0
NANDF_CS1
NANDF_CS2
NANDF_CS3
F15
C16
A17
D16
NANDF_ALE
NANDF_CLE
NANDF_WP_B
NANDF_RB0
A16
C15
E15
B16
NANDF_D0
NANDF_D1
NANDF_D2
NANDF_D3
NANDF_D4
NANDF_D5
NANDF_D6
NANDF_D7
A18
C17
F16
D17
A19
B18
E17
C18
SD4_CLK
SD4_CMD
E16
B17
SD4_DAT0
SD4_DAT1
SD4_DAT2
SD4_DAT3
SD4_DAT4
SD4_DAT5
SD4_DAT6
SD4_DAT7
D18
B19
F17
A20
E18
C19
B20
D19
AUD_MCLK_T
1
2
3
4
1
close to CPU
R16S
AUD_MCLK
SD2_WP
2
1
2
1
C15S
GND_136
+GND
AUD_CLK
50 ohm trace
49.9, 1%
C
SD2_CD
PCIE_PWRON
RGMII_INT
SD2_CD
GND_130
SD/MMC
HRS DM1AA-SF-PEJ(21)
D
SD2_CLK
2
1
1
2
C13S
2
0.1uF, 6.3V, X5R
+GND
R17S
10k, 1%
NVCC_GPIO
External SD card
GND_131
W5
V6
U7
U6
W6
W4
U5
T7
T6
V5
1
+GND
4 GByte MicroSD (Sandisk SDSDQ-4096)
SD2_DAT3
SD2_CMD
KEY_COL0
KEY_ROW0
KEY_COL1
KEY_ROW1
KEY_COL2
KEY_ROW2
KEY_COL3
KEY_ROW3
KEY_COL4
KEY_ROW4
note double-up on this pin
ambiguous if one is better than the other, but no harm to wire up both
(one BSP uses P5, another uses V21)
1
GND_135
+GND
1
2
3
4
5
6
7
8
9
WP
CD_W
CD
0
U20
W20
+GND
1
Q12S
2N7002W
GND_128
DAT3/RSV
CMD
GND
VCC
CLK
GND
DAT0/DAT
DAT1
DAT2
WP
CD_WP_COM
CD
CASE
ENET_TXD0
ENET_TXD1
C16S
2200pF, X7R, 50V, 10% (DNP)
GND_137
2
SD3_DAT0
SD3_DAT1
JP10S
W21
W22
2
D
S
G
AUK TFC08W01-HC-H
C
ENET_RXD0
ENET_RXD1
3
2
1
SD3_CLK
NT10S
SD2_CMD
SD2_CLK
SD2_DAT0
SD2_DAT1
SD2_DAT2
SD2_DAT3
0.1uF, 6.3V, X5R
Novena PVT1 firmware
R14S
10k, 1%
2
+GND
SD3_DAT2
SD3_DAT3
SD3_CMD
1
2
1
1
2
C12S
GND_127
1
2
3
4
5
6
7
8
R13S
100, 1%
F19
C21
A22
E20
A23
B22
2
49.9, 1% (DNP)
2
1
DAT2
CD/DAT3
CMD
VDD
CLK
VSS
DAT0
DAT1
2
2
1
1
0.1uF, 6.3V, X5R
NT11S
C11S
2
4.7uF, 10V, X5R, 10%
B
J10S
SD2_CMD
SD2_CLK
SD2_DAT0
SD2_DAT1
SD2_DAT2
SD2_DAT3
2
1
4
SDCARD_VDD
support 200mA max
R20S
1
1
3
D
note: this is a high speed line at 125 MHz, route as 50 ohms
1
S
Q11S
FDN304P
RGMII_REF_CLK
OTG_ID
RGMII_INT
2
2
+3.3V
300, 1%
3
GPT_CMPOUT3
G
SD3_RST_INV
P3.3V_DELAYED_25
RGMII_MDC
RGMII_MDIO
2
1
100k, 1%
V20
V23
U21
V22
W23
V21
4
1
ENET_MDC
ENET_MDIO
ENET_CRS_DV
ENET_REF_CLK
ENET_RX_ER
ENET_TX_EN
3
1
2
SD1_CMD
SD1_CLK
SD1_DAT0
SD1_DAT1
SD1_DAT2
SD1_DAT3
2
2
R12S
2
B21
D20
A21
C20
E19
F18
2
1
2
2
+GND
A
+2.5V
R21S
1
1
GPT_CMPOUT1
GPT_CLKIN
GPT_CAPIN1
FPGA_EXP_ON
GND_129
P2.5V_VGEN5_6
2
0.01uF, 10V, X5R, 10%
8
1
SD3_RST_N
AUD_CLK
1
NVCC_ENET
G
S
1
R11S
68k, 1%
2
D
1
2
2
Q10S
2N7002W
C10S
A
7
2
1
3
1
1
1k, 1%
6
U100_5
iMX6Q - MCIMX6Q5EYM12AC
+3.3V
1
2
NVCC_SD1
R10S
2
2
5
NVCC_SD2
Internal microSD card (main boot)
4
NVCC_SD3
1
D
E
Copyrights: CC-BY-SA 3.0
Patents: Apache 2.0
Copyright 2014 Andrew "bunnie" Huang
Sheet: /U_07sdcard/
File: 07sdcard.sch
Novena
Title: 07sdcard
PVT2-A
Size: B
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
2
3
4
5
6
7
Rev:
Id: 7/16
8
1
2
3
4
5
6
7
8
9
10
11
R10U
1
2
1
+3.3V
C10U
4.7uF, 10V, X5R, 10% (DNP)
R12U
10k, 1%
1
0 ohm (DNP)
2
GND_146
2
A
GND_152
+GND
4
+GND
DIFFPAIR
DIFFPAIR
GND_140
+GND
+GND
+GND
2
GND
2
D12U
RCLAMP0502B
C
2
2
R22U
680, 1%
1
GND_148
1
1
1
2
2
1
2
1
2
10k, 1%
R18U
1
2
1
R19U
1
2
10k, 1%
2
1
2
USB_PWREN3_N
USB_OVERCUR3_N
10k, 1%
P3.3V_DELAYED_34
+3.3V
internal pullup
MASTERHUB_RESET
+GND
1
2
1
R21U
10k, 1%
P3.3V_DELAYED_45
R23U
GND_151
2
RESETBMCU
+3.3V
0 ohm
R27U
1
+GND
1
2
1
2
USB_HUB1_RST
R26U
1k, 1%
C
1
3
2
10k, 1%
2
1
low-active power switches
2
1
R17U
1
GND
X1
X2
AVDD
DM3
DP3
AVDD
GND
DM4
DP4
GREEN4
AMBER4
use explicit reset line to reboot USB ethernet
USB ethernet has no power control
K1
K2
GND_139
+GND
1
1
2
2
GND_155
USB_ETH_N
USB_ETH_P
36
35
34
33
32
31
30
29
28
27
26
25
AMBER2
GREEN2
DVDD
AMBER3
GREEN3
PWREN3#
OVCUR3#
PWREN4#
OVCUR4#
TEST
RESET#
SEL48
GND_153
2
USB_NETS
USB_NETS
AUK USB-1X04-SR-BK-S-H
+3.3V
R16U
1
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
B
P3.3V_DELAYED_35
2
DIFFPAIR
DIFFPAIR
USB_H1_D_N
USB_H1_D_P
USB_EXT1_N
USB_EXT1_P
ports 2/3 are non-removable
2
2
USB_NETS
USB_NETS
USB_NETS
USB_NETS
USB_NETS
USB_NETS
AVDD
GND
DM0
DP0
DM1
DP1
AVDD
GND
DM2
GL852GC-MNG
LQFP48
DP2 GL852GC
RREF
AVDD
C20U
2
3
1
2
3
4
5
6
7
8
9
10
11
12
Amber1/Green4 NC => Port 1 is CDP
+GND
1
1
1
2
2
+GND
C19U
GND_145
1
A
2
2
1
C23U
1
GND_176
2
2
2
1
1
1
R20U
C25U 100, 1%
1
2
3
4
P5.0V_USBEXT1
P11U
C22U
2
2
2
1
C21U
0.1uF, 25V, X5R
1
RT9711BGB
1
+GND
3A 120 ohm
1
GND_157
2
BLM18KG121
1
4
2
1
2
VIN
1
1
0.1uF, 25V, X5R
3
GND
+GND
5
2
GND_175
K1
K2
1
2
1
1
A
K
D15U
RSA5M
GND_141
VOUT
2
0.1uF, 25V, X5R
FCI 10103594-0001LF
D11U
RCLAMP0502B
100, 1% (DNP)
2
1
R42U
100k, 1%
1
OTG_ID
1
A
R41U
2
+3.3V
D10U
RSA5M
+5V
FLG
GND
EN
+3.3V
0.1uF, 6.3V, X5R
U11U
D16U
RSA5M
P3.3V_DELAYED_32
V33
V5
AMBER1
GREEN1
SEL27
PWREN1#
OVCUR1#
PWREN2#
OVCUR2#
PGANG
DVDD
PSELF
K
U10U
L11U
P5.0V_DELAYED_3
USB_OVERCUR1_N1
2
USB_PWREN1_N 3
0
P3.3V_DELAYED_43
1
2
2
2
VBUS
DD+
ID
GND
K
USB_NETS
DIFFPAIR
USB_NETS
DIFFPAIR
B
1
2
3
4
5
PAD
OTG_VBUS
USB_OTG_N
USB_OTG_P
48
47
46
45
44
43
42
41
40
39
38
37
1
R15U
10k, 1%
1
1
P10U
1.0uF, 25V, 20% X5R
2
Micro-B
R14U
10k, 1%
1
1
1
2
+GND
self-powered
2
2
1
C18U
C11U
GND_147
2
1
2
1
C17U
2
0.1uF, 6.3V, X5R
1
2
1
C16U
2
0.1uF, 6.3V, X5R
1
2
1
C15U
2
1
1
2
2
1
1
2
2
1
C14U
USBA_P3.3VA
1
100k, 1%
2
+3.3V
C13U
0.1uF, 6.3V, X5R
P3.3V_DELAYED_36
+GND
0.1uF, 6.3V, X5R
OTG port - allow B mode only
C12U
GND_144
0.1uF, 6.3V, X5R
3A 120 ohm
2
2
2
2
1
BLM18KG121
+3.3V
1
0.1uF, 6.3V, X5R
L10U
1
1
4.7uF, 10V, X5R, 10%
0 ohm (DNP)
P3.3V_DELAYED_31
1
2
internal pullup
2
R11U set for individual power management
1
2
1
USB_PWREN1_N
USB_OVERCUR1_N
R13U
1
2
1
10uF, 10V, X5R, 20% (DNP)
2
2
+GND
2
Primary function hub
A
P3.3V_DELAYED_33
2
1
+5V
0.1uF, 6.3V, X5R
P5.0V_DELAYED_2
GND_156
0 ohm (DNP)
1
1
13
14
15
16
17
18
19
20
USB_NETS USB_OPT_NDIFFPAIR21
USB_NETS USB_OPT_PDIFFPAIR22
23
24
+GND
SoC interface
2
+GND
1
2
OSC2
D
DIFFPAIR
DIFFPAIR
+GND
1
GND_149
2
C31U
GND_150
1
12.0000 MHz (NDK NX5032GB-12MHZ-STD-CSK-5, 30ppm, 8pF)
+GND
C32U
2
USB_NETS USB_PCI_N
USB_NETS USB_PCI_P
USB_OTG_N
USB_OTG_P
VDDUSB_CAP
OSC1
8.2 pF, NP0
E9
B6
A6
AMBER3/4 PD => 4 DP declared
Y10U
1
8.2 pF, NP0
1
1
2
2
1
2
GND_138
F9
USB_OTG_VBUS
USB_OTG_DN
USB_OTG_DP
C34U
2
1
C33U
USB_OTG_CHD_B
B8
0.22uF, 6.3V, X5R 10%
i.MX6Q - USB
D
C35U
1
2
+GND
1
2
GND_143
1
1
C28U
1
U100_6
iMX6Q - MCIMX6Q5EYM12AC
2
USB_VBUS
2
0 ohm
1
1
4.7uF, 10V, X5R, 10%
2
1
2
2
1
2
0 ohm
2
2
+5V
OTG_VBUS R43U
2
R25U
P5.0V_SWBST_3
VDDUSB_CAP
R24U
10k, 1%
GND_154
10uF, 10V, X5R, 20%
+GND
0.22uF, 6.3V, X5R 10%
USB_H1_D_P
USB_H1_D_N
Slave function hub
1
C36U
E
1
C27U
GND_142
2
+GND
GND_169
K1
K2
+GND
2
GND
G
2
D14U
RCLAMP0502B
R37U
680, 1%
1
GND_162
2
1
1
1
2
2
1
1
2
10k, 1%
2
1
2
10k, 1%
SLAVEHUB_RESET
+3.3V
R36U
10k, 1%
G
GND_165
+GND
P3.3V_DELAYED_44
R44U
1
2
1
2
RESETBMCU
+3.3V
0 ohm
1
GND_170
1
2
1
2
USB_HUB2_RST
R45U
1k, 1%
0 ohm (DNP)
Amber1/Green4 NC => Port 1 is CDP
1
13
14
15
16
USB_NETS USB_KBD_NDIFFPAIR17
USB_NETS USB_KBD_PDIFFPAIR18
19
20
USB_NETS USB_VID_N DIFFPAIR21
USB_NETS USB_VID_P DIFFPAIR22
23
24
P3.3V_DELAYED_40
2
USB_PWREN7_N
USB_OVERCUR7_N
USB_PWREN8_N
USB_OVERCUR8_N
R46U
+GND
low-active power switches
R35U
1
+GND
3
2
1
2
USB_MOUSE_N DIFFPAIR
USB_MOUSE_P DIFFPAIR
+GND
R34U
36
35
34
33
32
31
30
29
28
27
26
25
1
USB_NETS
USB_NETS
AUK USB-1X04-SR-BK-S-H
GND_167
AMBER2
GREEN2
DVDD
AMBER3
GREEN3
PWREN3#
OVCUR3#
PWREN4#
OVCUR4#
TEST
RESET#
SEL48
1
4
F
1
USB_NETS
USB_NETS
C47U
1
3
USB_EXT2_N
DIFFPAIR
USB_EXT2_P
DIFFPAIR
AVDD
GND
DM0
DP0
DM1
DP1
AVDD
GND
DM2
GL852GC-MNG
LQFP48
DP2 GL852GC
RREF
AVDD
+GND
2
USB_NETS
USB_NETS
USB_OPT_N
USB_OPT_P
USB_EXT2_N
DIFFPAIR
USB_EXT2_P
DIFFPAIR
1
2
3
4
5
6
7
8
9
10
11
12
C46U
GND_159
2
2
+GND
GND
X1
X2
AVDD
DM3
DP3
AVDD
GND
DM4
DP4
GREEN4
AMBER4
1
1
C49U
2
GND_177
1
2
2
2
1
2
3
4
1
P5.0V_USBEXT2
P13U
C48U
1
RT9711BGB
2
+GND
2
GND_171
2
3A 120 ohm
0.1uF, 25V, X5R
4
2
1
BLM18KG121
1
VIN
1
1
5
1
VOUT
2
FLG
GND
EN
2
USB_OVERCUR8_N 1
2
USB_PWREN8_N 3
A
U14U
+3.3V
0.1uF, 6.3V, X5R
L14U
P3.3V_DELAYED_38
V33
V5
AMBER1
GREEN1
SEL27
PWREN1#
OVCUR1#
PWREN2#
OVCUR2#
PGANG
DVDD
PSELF
D17U
RSA5M
K
+5V
48
47
46
45
44
43
42
41
40
39
38
37
1
U13U
P5.0V_DELAYED_5
1.0uF, 25V, 20% X5R
2
R33U
10k, 1%
1
1
F
R32U
10k, 1%
2
C38U
2
1
1
2
+GND
2
1
2
2
C45U
GND_161
2
1
4.7uF, 10V, X5R, 10%
1
2
1
C44U
2
0.1uF, 6.3V, X5R
1
1
2
C43U
2
C42U
0.1uF, 6.3V, X5R
1
1
2
2
0.1uF, 6.3V, X5R
1
1
2
2
1
1
2
2
C41U
USBB_P3.3VA
1
100k, 1%
2
+3.3V
C40U
0.1uF, 6.3V, X5R
P3.3V_DELAYED_41
C39U
+GND
GND_158
0.1uF, 6.3V, X5R
3A 120 ohm
1
2
1
2
1
BLM18KG121
2
1
+3.3V
2
P3.3V_DELAYED_37
0.1uF, 6.3V, X5R
L13U
1
2
1
2
+GND
R29U set for individual power management
1
2
1
0 ohm (DNP)
GND_166
2
self-powered
1
USB_PWREN5_N
USB_OVERCUR5_N
USB_PWREN6_N
USB_OVERCUR6_N
R31U
+3.3V
C37U
4.7uF, 10V, X5R, 10% (DNP)
R30U
10k, 1%
2
2
+GND
2
0.22uF, 6.3V, X5R 10%
2
GND_160
1
1
0 ohm (DNP)
0.1uF, 6.3V, X5R
2
1
+5V
P3.3V_DELAYED_39
2
1
1
1
Amber1/Green4 NC => Port 1 is CDP
2
R28U
P5.0V_DELAYED_4
10uF, 10V, X5R, 20% (DNP)
2
1
1
VBUS_HOST
2
4.7uF, 10V, X5R, 10%
E
E10
F10
D10
USB_H1_DP
USB_H1_DN
USB_H1_VBUS
P3.3V_DELAYED_42
GND_173
+GND
1
2
3
4
2
12.0000 MHz (NDK NX5032GB-12MHZ-STD-CSK-5, 30ppm, 8pF)
GND_174
+GND
+GND
6
7
8
GND_164
+GND
C53U
Sheet: /U_08usb/
File: 08usb.sch
1
C52U
GND_172
5
2
1
USB_OVERCUR7_N
OSC2
GND_163
2
3
GND
OSC1
+GND
C54U
Copyright 2014 Andrew "bunnie" Huang
Novena PVT2-A
Title: 08usb
2
FLG
EN
H
1
P5.0V_KBD
AMBER3/4 PD => 4 DP declared
Y11U
8.2 pF, NP0
2
1
1
2
C56U
5
1
1
VOUT
2
C55U
2
2
1
1
USB_PWREN7_N
VIN
2
4
1
8.2 pF, NP0
Patents: Apache 2.0
1.0uF, 25V, 20% X5R
Copyrights: CC-BY-SA 3.0
1.0uF, 25V, 20% X5R
U16U
RT9706
to front panel USB breakout via 30-pin FFC
2
10uF, 10V, X5R, 20%
H
1
1
2
2
C51U
1
USB_OVERCUR6_N
2
3
+GND
2
FLG
R38U
10k, 1%
GND_168
1
GND
P5.0V_MOUSE
1
EN
2
5
2
1
VOUT
2
2
VIN
R40U
10k, 1%
2
USB_PWREN6_N
R39U
10k, 1%
2
4
1
U15U
RT9706
10uF, 10V, X5R, 20%
+3.3V
1
+5V
1
1
P5.0V_DELAYED_6
Size: C
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
9
10
Rev:
Id: 8/16
11
1
2
3
4
5
A
male
female
P5.0V_DELAYED_8
+5V
A
HD
Charger
Mainboard
male
female
SATA connector arrangement
R10H
2
1
2
1
100k, 1%
C10H
1
2
1
2
P3.3V_DELAYED_48
1.0uF, 25V, 20% X5R
2
1
+3.3V
P3.3V_DELAYED_47
2
Q10H
FDN304P
1
G
3
3
D
2
R12H
10k, 1%
R11H
10k, 1%
1
A
K
Optimized for use with SSDs
1
1
For boot: compatible ONLY with SATA-II (3Gbps) drives
R14H
330, 1%
+GND
2
B
D10H
1
2
C16H
2
G13
SATA_RXP
SATA_RXM
B14
A14
SATA_TXM
SATA_TXP
B12
A12
SATA_RX_P DIFFPAIR
SATA_NETS
SATA_RX_N
100 ohm
SATA_TX_N DIFFPAIR
SATA_NETS
SATA_TX_P
DIFFPAIR
100 ohm
SATA_REXT
2
C21H
C14 SATA_REXT
1
2
1
2
C18H
2
1
2
1
1
2
1
2
+3.3V
1
P3.3V_DELAYED_46
DIFFPAIRSATAC_RX_P
C13H
100 ohm16
DIFFPAIR
SATAC_RX_N SATA_NETS
100 ohm17
SATA_NETS18
10nF, X7R, 50V 10%
100 ohm19
SATA_NETS
100 ohm20
SATA_NETS21
DIFFPAIRSATAC_TX_N
22
10nF, X7R, 50V 10%
1
C22H
2
22uF, 10V, X5R, 20%
1
1
2
2
1
1
2
2
10uF, 10V, X5R, 20%
C11H
C14H
SATA_NETS
10nF, X7R, 50V 10%
100 ohm
1
1
+GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
1
2
C19H
+VDD
2
GND_182
C17H
SATA_VP
SATA_VPH
C12H
VDD_HIGH_CAP_3
1
1
2
1
2
DIFFPAIR
SATAC_TX_P
GND_181
+GND
+12V
+12V
+12V
GND
OPT
GND
+5V
+5V
+5V
GND
GND
GND
+3.3V
+3.3V
+3.3V
C
GND
B+
BGND
AA+
GND
MOLEX 47018-2000 female
10nF, X7R, 50V 10%
1
R15H
191, 1%
+GND
2
GND_180
2
0.22uF, 6.3V, X5R 10%
i.MX6Q - SATA
P5.0V_SATA
J10H
2
1
0.22uF, 6.3V, X5R 10%
1
1
2
1
1
2
+GND
100 ohm
DIFFPAIRSATA_NETS
+VDD
G12
C20H
GND_179
P
8
7
6
5
D
D
D
D
VDDSOC_CAP_2
C15H
GND_178
+GND
2
4.7uF, 10V, X5R, 10%
C
S
S
S
G
10uF, 10V, X5R, 20%
Q12H
1
2
3
4
Si4435DY
U100_7
iMX6Q - MCIMX6Q5EYM12AC
2
4.7uF, 10V, X5R, 10%
+5V
22uF, 10V, X5R, 20%
1
1
GND_184
P5.0V_DELAYED_7
B
R13H
10k, 1%
2
+GND
2
2
GND_183
2
Q11H
2N7002W
2
G
HDD activity LED
APT1608SGC green
1
S
SATA_PWRON
D
2
2
1
1
+3.3V
S
1
uses M-F extender combo cables
D
D
Copyright 2014 Andrew "bunnie" Huang
Sheet: /U_09sata/
File: 09sata.sch
Title: Novena
09sata
1
Copyrights:
CC-BY-SA 3.0
2
Patents: Apache
2.0
3
PVT2-A
Size: A
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
4
Rev:
Id: 9/16
5
1
2
3
4
5
6
7
8
9
10
11
A
A
GND_192
4
8
14
15
22
37
53
48
2
2
33
MFB_3/TXD1
MFB_4/TXD0
32
31
MFB_5/REF50M
MFB_6/RXD1
MFB_7/RXD0
30
29
28
GPIO_0/PME
27
GPIO_1
GPIO_2
26
25
SD
7
R19E
2
2
1
2
40
38
39
22 ohm, 1%
R20E
1
2
1
2
22 ohm, 1%
EEDIO
EECK
EECS
1
93C66 (DNP)
2
2
1
C16E
GND_194
+GND
93C56 or 93C66 EEPROM
GND_202
+GND
19
MFA_2/RMII_N
Optional
EN100_LINK
J11E
MFA_1/MDIO
18
MFA_0/MDC
17
2
0.1uF, 25V, X5R
test point (DNP)
1
1
2
2
1
1
49.9, 1%
DIFFPAIR
DIFFPAIR
+GND
R21E
1
test point (DNP)
R22E
C17E
+3.3V
1
20
24
36
49
+GND
+GND
GND_199
+GND
GND_200
+GND
D
TRD4+
C7 - TRP4+
TRCT4
TRD4-
L4
GRN_K
L5
G/O_A
L6
330, 1%
ORG_K
EN100_LINK
EN100_USB_ACT
L2
YEL_K
R25E
L1
YEL_A
R24E
2
1
2
1
2
2
2
1
1
2
1
1
R29E
49.9, 1%
1
1
2
R28E
E
C20E
2
2
+GND
2
2
2
2
1
1
1
1
2
C19E
GND_215
UDE CORP 26-21024JA13-1
1
1
2
C25E
RX-
C26E
2
1
1
2
2
1
1
2
2
1
1
2
2
GND_187
3A 120 ohm
C24E
0.1uF, 6.3V, X5R
C28E
0.1uF, 6.3V, X5R
1
1
2
GND_213
C23E
R27E
49.9,
1%
0.1uF, 25V,
X5R
2
4.7uF, 10V, X5R, 10%
+GND
2
C27E
GND_212
0.1uF, 6.3V, X5R
1
2
+3.3V
1
P3.3V_DELAYED_49
2
+GND
4.7uF, 10V, X5R, 10%
1
1
2
2
GND_210
4.7uF, 10V, X5R, 10%
+GND
4.7uF, 10V, X5R, 10%
1
1
2
2
0.1uF, 6.3V, X5R
GND_211
C22E
EN100_A1.8V
2
1
1
1
0.1uF, 25V, X5R
49.9, 1%
1
BLM18KG121
3A 120 ohm
C21E
R26E
49.9, 1%
2
2
1
11
64
51
52
6
59
60
EN100_D1.8V
2
TRD3+
C5 - TRP3TRCT3
TRD3-
330, 1%
L11E
2
1
R4
R6
R5
C8 - TRP4-
+GND
+3.3V
BLM18KG121
RX+
C6 - TRP2-
GND_196
EN100_A3.3V
1
TRD2+
C3 - TRP2+
TRCT2
TRD2-
TX-
P3.3V_DELAYED_52
3.3V to 1.8V On-chip Regulator
L10E
R3
R1
R2
R11
R12
R10
terminate unused, floating pairs
E
TX+
C4 - TRP3+
GND_197
J12E
1
2
EN100_TXO_P
EN100_TXO_N
1
1
2
2
2
1
C15E
1
AX88772B
16
44
2
1
C18E
2
0.1uF, 25V, X5R (DNP)
EN100_RESET_N
2
1
VCCK
VCCK
VCCK
VCCK
R23E
47k, 1%
2
2
D
0.1uF, 6.3V, X5R
1
1
1
4.7k, 1%
1
VCC18A
VCC18A
VCC18A_PLL
1
R18E
4
3
2
1
DO
DI
SK
CS
V18F
+3.3V
GND
ORG
NC
VCC
VCC3IO
VCC3IO
+3.3V
5
6
7
8
VCC3R3
VCC3A3
VCC33A_PLL
VCC33A_H
P3.3V_DELAYED_50
TRD1+
C1 - TRP1+
TRCT1
TRD1C2 - TRP1-
2
U11E
P3.3V_DELAYED_51
C14E
2
+GND
DIFFPAIR
DIFFPAIR
1
GND_191
JP10E
R8
R7
R9
short CT1, CT2 for auto-MDIX
1
Reset Circuit
+3.3V
R16E
49.9, 1%
EXTWAKEUP_N
EN100_RXI_P
EN100_RXI_N
EN100_A3.3V_2
1
23
test point (DNP)
2
12.1k, 1%
1
1
J10E
1
49.9, 1%
RSET_BG
R15E
2
5
2
2
C
1
2
1
1
1
AX88772B
+GND
C13E
1
+GND
X2
X1
GND_195
2
R17E
GND_189
61
62
0.1uF, 25V, X5R 49.9, 1%
+GND
1
GND_198
TCLK_EN
TCLK_0
TCLK_1
1
C
43
42
41
1
MFB_2/TXEN
1
34
2
MFB_1/CRSDV
2
RREF
RJ-45 Connector + Tranformer
2
58
12.1k, 1%
C12E
2
35
33pF, NP0
MFB_0
GND_214
0.1uF, 25V, X5R
TEST1
TEST0
C11E
+GND
1
46
47
1
EN100_TXO_N
EN100_TXO_P
1
13
12
1
TXON
TXOP
RESET_N
1
OSC1
OSC2
GND18A
GND18A
GND
GND
GND
GND
GND18A
EN100_RXI_N
EN100_RXI_P
1
2
10
9
2
2
1
RXIN
RXIP
Y10E R12E
1M, 1%
2
1
EN100_XTL25P
EN100_XTL25N
4.7uF, 10V, X5R, 10%
R14E
+GND
2
3
MFA_3/PHY_N
EN100_RESET_N45
GND_193
GND3R3
1
1
EN100_USB_ACT
21
XTL25P
XTL25N
2
0 ohm
C10E
B
2
2
DM
DP
1
USB_ETHI_P
2
1
V_BUS
57
56
33pF, NP0
R13E
1
50
25.0000 MHz, 30ppm, 20pF, ESR <70 ohm (CTS 445C33E25M00000)
USB_ETH_P
2
0 ohm
2
USB_NETS
4.7k, 1%
DIFFPAIR
DIFFPAIR
USB_NETS
2
2
3.3pF, NP0 (DNP)
USB_ETHI_N
2
1
GND33A_PLL
2
1
R11E
1
GND33A_H
R10E
1
USB_ETH_N
GND18A_PLL
U10E
+5V
B
54
P5.0V_DELAYED_9
55
63
+GND
GND_201
+GND
F
F
Power and by-pass capacitors
Close to pin 16.44
Close to pin 6.59.60
EN100_A3.3V_3
+3.3V
P3.3V_DELAYED_53
+GND
GND_209
+GND
1
1
GND_185
+GND
1
2
C32E
2
1
2
C31E
2
2
2
1
C30E
0.1uF, 6.3V, X5R
GND_186
0.1uF, 6.3V, X5R
1
0.1uF, 6.3V, X5R
1
2
1
C29E
2
0.1uF, 6.3V, X5R
+3.3V
GND_208
+GND
G
G
Close to pin 20.24.36.49
Close to pin 1.11.64
+GND
+GND
1
1
2
1
2
GND_203
C38E
C39E
2
1
2
1
1
2
GND_204
C37E
0.1uF, 6.3V, X5R
+GND
2
1
1
2
GND_188
0.1uF, 6.3V, X5R
+GND
C36E
2
1
1
2
GND_205
C35E
0.1uF, 6.3V, X5R
+GND
2
1
1
2
2
GND_206
C34E
0.1uF, 6.3V, X5R
+GND
C33E
0.1uF, 6.3V, X5R
GND_207
EN100_A1.8V
0.1uF, 6.3V, X5R
1
1
2
2
0.1uF, 6.3V, X5R
EN100_D1.8V
GND_190
+GND
H
H
Copyright 2014 Andrew "bunnie" Huang
Novena PVT2-A
Sheet: /U_10ethernet100/
File: 10ethernet100.sch
Copyrights: CC-BY-SA 3.0
1
2
3
4
5
6
7
8
Title: 10ethernet100
Patents: Apache 2.0
Size: C
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
9
10
Rev:
Id: 10/16
11
1
2
3
4
5
6
7
8
EN1G_1.2VA_2
RGM_CLK
GND_216
1
2
2
1
2
1
1
RGMII_MDIO
RGMII_MDC
RGMII_RXCLKRGM_CLK
+2.5V
1
2
1
RGMII_RXDV RGM_CLK
RGMII_RXD0 RGM_CLK
RGMII_RXD1 RGM_CLK
2
10uF, 10V, X5R, 20%
C18G
RGMII_TXENRGM_CLK
2
1
2
GND_226
+GND
0.1uF, 6.3V, X5R
GND_224
1
GND_235
+GND
C22
F20
E21
A24
RGMII_TX_CTL
C33G
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
C23 RGMII_TXEN
C
RGMII_RXC
B25 RGMII_RXCLK_D
RGMII_RD0
RGMII_RD1
RGMII_RD2
RGMII_RD3
C24
B23
B24
D23
RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXD3
D22 RGMII_RXDV
1
iMX6Q - MCIMX6Q5EYM12AC
P3.3V_DELAYED_55
2
1
C36G
C37G
+3.3V
GND_231
+GND
R16G
P5.0V_DELAYED_10
2
R17G
1
2
1
1
2
D
1
10k, 1%
R18G
10k, 1%
U11G
EN1G_P1.2V
FB
GND
SW
GND
1
2
3
7
+1.2V
L12G
1
2
1
2
2.2uH, coilcraft MSS5131-222ML
2
C40G
2
+GND
LMR10510YSD
C29G
4.7uF, 10V, X5R, 10%
K
1
GND_232
A
2
GND_229
D10G
CDBM140-G
+GND
C27G
C28G
1
1
1
1
2
1
EN
VINA
VIND
10k, 1%
2
1
1
2
2
2
6
5
4
2
GND_233
RGMII_TD0
RGMII_TD1
RGMII_TD2
RGMII_TD3
2
+GND
0.1uF, 6.3V, X5R
1
1
2
GND_234
2
C39G
+GND
D21 RGMII_TXCLK_D
1
+GND
2
RGMII_RXD2 RGM_CLK
RGMII_RXD3 RGM_CLK
1
+1.2V
RGMII_TXC
2
0.1uF, 6.3V, X5R
EN1G_P1.2V_4
+5V
0.1uF, 6.3V, X5R
1
1
2
+2.5V
2
1
C26G
B
i.MX6Q - RGMII
C17G
P2.5V_VGEN5_8
RGMII_RX_CTL
C22G
P2.5V_VGEN5_9
2
1
2
RGMII_REF_CLK
+3.3VA
1
RGMII_TXCLK_D
2
1
0 ohm (DNP)
EN1G_3.3VA
2
1
R13G
4.7k, 1%
KSZ9021RN
2
1
1
2
+GND
2
1
1
2
2
GND_223
R29G
0 ohm
R30G
RGMII_TXCLK
2
1
2
1
1
1
2
2
C21G
RGMII_TDEL5B
RGM_CLK
U100_8
36
35
34
33
32
31
30
29
28
27
26
25
MDC
RX_CLK/PHYAD2
DVDDH
RX_DV/CLK125_EN
RXD0/MODE0
RXD1/MODE1
DVDDL
VSS
RXD2/MODE2
RXD3/MODE3
DVDDL
TX_EN
0.1uF, 6.3V, X5R
+GND
+1.2V
2
C25G
GND_220
0.1uF, 6.3V, X5R
1
1
2
1
1
2
2
2
2
1
BLM18KG121
C24G3A 120 ohm
10uF, 10V, X5R, 20%
1
2
2
0.1uF, 6.3V, X5R
C23G
1
1
+3.3V
2
10uF, 10V, X5R, 20%
P3.3V_DELAYED_54
1
2
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
2
2
330, 1%
2
2
0 ohm
0.1uF, 6.3V, X5R
1
2
2
1
2
R19G
R28G
0 ohm
+GND
EN1G_P1.2V_5
+3.3V
place close to U10G
1
1
1
GND_219
GND_228
330, 1%
1
C35G
2
2
1
C34G
2
1
2
1
+GND
0 ohm (DNP)
C20G
+GND
P3.3V_DELAYED_56
R15G
1
D
GND_236
RGMII_INT
RGMII_REFCLK_T R21G
AVDDH
TXRXP_A
TXRXM_A
AVDDL
TXRXP_B
TXRXM_B
TXRXP_C
TXRXM_C
AVDDL
TXRXP_D
TXRXM_D
AVDDH
1
0.1uF, 25V, X5R
1
R14G
1
C19G
2
EN1G_ACT
4.7uF, 10V, X5R, 10%
EN1G_LINK
L2
L1
1
2
3
4
5
6
7
8
9
10
11
12
DIFFPAIR
DIFFPAIR
+3.3VA
R11G
4.7k, 1%
VSS_PS
DVDDL
LED2/PHYAD1
DVDDH
LED1/PHYADD
DVDDL
TXD0
TXD1
TXD2
TXD3
DVDDL
GTX_CLK
DIFFPAIR
DIFFPAIR
DIFFPAIR
R12G
13
14
10uF, 10V, X5R, 20%
EN1G_LINK 15
16
EN1G_ACT 17
18
RGM_CLK RGMII_TXD0
19
RGM_CLK RGMII_TXD1
20
RGM_CLK RGMII_TXD2
21
RGM_CLK RGMII_TXD3
22
23
RGM_CLK RGMII_TXCLK
24
TXRXB_N
TXRXC_P
TXRXC_N
EN1G_3.3VA_4
UDE CORP 26-21024JA13-1
L11G
0.1uF, 6.3V, X5R
1
1
2
2
DIFFPAIR
DIFFPAIR
DIFFPAIR
TXRXD_P
TXRXD_N
L4
L5
L6
PAD 49
48
ISET
4.99k, 1%
AVDDH 47
XI 46
XO 45
AVDDL_PLL 44
LDO_O 43
RESET_N 42
CLK125_MD0/LED_MODE 41 AUD_CLK
DVDDH 40
DVDDL 39
INT_N 38
MDIO 37
0.1uF, 6.3V, X5R
1
1
2
1
1
2
2
2
TXRXA_N
TXRXB_P
C8 - TRP4-
YEL_K
YEL_A
U10G
TXRXA_P
C6 - TRP2-
GRN_K
G/O_A
ORG_K
+GND
1
C
C16G
GND_218
1
R11
R12
R10
+GND
C15G
2
TRD4+
C7 - TRP4+
TRCT4
TRD4-
C4 - TRP3+
C14G
GND_217
C2 - TRP1-
C3 - TRP2+
+1.2V
2
R4
R6
R5
BLM18KG121
C13G
3A 120 ohm
+3.3VA
0.1uF, 6.3V, X5R
TRD3+
C5 - TRP3TRCT3
TRD3-
+GND
EN1G_1.2VA
1
R3
R1
R2
GND_227
2
1
TRD2+
TRCT2
TRD2-
2
1
2
R8
R7
R9
1
2
TRD1+
C1 - TRP1+
TRCT1
TRD1-
+GND
10uF, 10V, X5R, 20%
22uF, 6.3V, X5R, 20%
JP10G
GND_225
33pF, NP0
EN1G_3.3VA_2
1
2
2
1
2
0 ohm
RGM_CLK
2
1
L10G
1
2
2
1
+1.2V
2
1
+2.5V
2
P2.5V_VGEN5_10
RGM_CLK
+2.5V
1
EN1G_P1.2V_2
B
1
RGM_CLK RGMII_TDEL5A
R20G
10k, 1% (DNP)
+GND
P2.5V_VGEN5_7
R26G
0 ohm (DNP)
1
2
1
2
+3.3VA
C11G
+GND
R27G
GND_238
1
EN1G_3.3VA_3
R25G
0 ohm (DNP)
2
2
2
Y10G
R10G
2.2M, 1%
2
1
1
RGMII_NRST
2
OSC1
OSC2
25.0000 MHz, 30ppm, 20pF, ESR <70 ohm (CTS 445C33E25M00000)
GND_222
RGMII_TDEL10
2
33pF, NP0
2
4.7uF, 10V,+GND
X5R, 10%
C31G
2
2
+GND
1
2
1
GND_237
1
2
2
RGM_CLK
2
1
RGMII_RXCLK_D
2
1
0 ohm
1
1
1
1
1
+GND
A
2
C10G
GND_221
R24G
RGMII_RXCLK
75 mA AVDDH (3.3V)
1
+1.2V
0.1uF, 6.3V, X5R
C12G
1
1
2
EN1G_P1.2V_3
1
2
R23G
0 ohm (DNP)
2
2
1
563 mA DVDDL (1.2V)
C30G
0.1uF, 6.3V, X5R
+1.2V
R22G
0 ohm (DNP)
1
1
A
1
2
37 mA from P2.5V_VGEN5
2
2
RGM_CLK RGMII_RDELAY
GND_230
E
10uF, 10V, X5R, 20%
10uF, 10V, X5R, 20%
+GND
E
Copyright 2014 Andrew "bunnie" Huang
Sheet: /U_11ethernetGbit/
File: 11ethernetGbit.sch
Novena PVT2-A
Title: 11ethernetGbit
1
2
3
4
Copyrights:
CC-BY-SA 3.0
5
Patents: Apache
2.0
6
Size: B
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
7
Rev:
Id: 11/16
8
1
2
3
4
5
6
7
R10X
A
1
2
A
2
1
C10X
2
3
10k, 1%
1
D
1
R20X
1
DIFFPAIR
PCIE_TXX_N
0.1uF, 6.3V, X5R
C26X
2
1
2
1
DIFFPAIR
PCIE_TXX_P
1
0.1uF, 6.3V, X5R
+GND
UIM_PWRON
1
1
2
2
G
1
22uF, 6.3V, X5R, 20%
1
2
2
1
2
2
1
0.1uF, 6.3V, X5R
1
4.7uF, 10V, X5R, 10%
+3.3V
GND_243
U10X
C4
C3
C2
C1
CC4
CLK
RST
VDD
CC8
I/O
VPP
VSS
C8
C7
C6
C5
1
2
GND_251
2
Note: no VPP provided by mainboard
seems to be NC for most modern SIM cards
SIM socket MOLEX 47308-0001
PCIE_WDIS_N
PCIE_RST
GND_246
+GND
MPCIE_3.3V_2
+3.3V
R16X
2
1
1
R17X
1
PCIE_WWAN_LED
PCIE_WLAN_LED
PCIE_WPAN_LED
2
1
2
330, 1%
R19X
1
2
1
2
R18X
1
2
1
2
330, 1%
D12X
A
K
USB_PCI_N
USB_PCI_P
1
+3.3V
1
SMB_SCL
SMB_SDA
C
MPCIE_3.3V_3
68k, 1%
D11X
2
A
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
0.1uF, 6.3V, X5R
GND
W_DISABLE_N
PERST_N
3.3VAUX
GND
1.5V
SMB_CLK
SMB_DATA
GND
USB_D_N
USB_D_P
GND
LED_WWAN_N
LED_WLAN_N
LED_WPAN_N
1.5V
GND
3.3VAUX
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
1
Q12X
FDN304P
C16X
+GND
2
1
2
UIM_C8
UIM_C4
GND
PE_RX0_N
PE_RX0_P
GND
GND
PE_TX0_N
PE_TX0_P
GND
GND
3.3VAUX
3.3VAUX
GND
RESVD
RESVD
RESVD
RESVD
B
P3.3V_DELAYED_59
APT1608SGC green
2
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
1
K
0 ohm 0201
C25X
GND_242
1
1
DIFFPAIR
PCIE_RXX_P
2
4
6
8
10
12
14
16
2
2
1
3.3VAUX
GND
1.5V
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
D
APT1608SGC green
1
2
WAKE_N
COEX1
COEX2
CLKREQ_N
GND
REFCLK_N
REFCLK_P
GND
3 R14X
2
S
100k, 1%
JP10X
1
3
5
7
9
11
13
15
2
D10X
2
PCIE_TX_N
DIFFPAIR
PCIE_TX_P
DIFFPAIR
2
2
0 ohm 0201
C22X
C15X
1
1
+1.5V
C14X
A
2
DIFFPAIR
PCIE_RXX_N
P1.5V_VGEN2_2
+GND
K
PCIE_DAT
PCIE_CLK
DIFFPAIR
PCIE_REFCLKX_P
1.5V up to 250 mA
Note deviation from PCIE spec of 375mA
C13X
GND_250
2
A3
B3
1
3
D
APT1608SGC green
PCIE_REXT
2
2
C28X
PCIE_TXM
PCIE_TXP
1
PCIE_DATX
PCIE_DATX
PCIE_VPH
2
1
G
1
PCIE_WAKE
DIFFPAIR
PCIE_REFCLKX_N
PCIE_DATX
G7
1
2
2
PCIE_RX_N
PCIE_RX_P
DIFFPAIR
PCIE_DAT
PCIE_DAT
PCIE_VPTX
B1
B2
PCIE_DAT
1
1
2
0.1uF, 6.3V, X5R
PCIE_RXM
PCIE_RXP
G8
2
1
1
C27X
PCIE_VP
DIFFPAIR
1
+GND
1
0.1uF, 6.3V, X5R
C21X
200, 1%
GND_241
C24X
PCIE_REXT
A2
2
+VDD
1
2
2
2
VDD_HIGH_CAP_4
0.1uF, 6.3V, X5R
C23X
2
+GND
PCIE_DATX
PCIE_CLKX
PCIE_CLKX
PCIE_CLK
1
1
2
DIFFPAIR
PCIE_REFCLK_P
2
0.1uF, 6.3V, X5R
1
1
2
2
1
1
2
GND_240
1
3A 120 ohm
1
2
2
2
1
BLM18KG121
1
1
1
0.1uF, 6.3V, X5R
C18X
H7
2
1
4.7uF, 10V, X5R, 10% 4.7uF, 10V, X5R, 10% 4.7uF, 10V, X5R, 10%
L10X
1A @ 3.3V per spec
C17X
2
S
Q11X
FDN304P
1
1
2
DIFFPAIR
PCIE_REFCLK_N
2
+3.3V
test point (DNP)
49.9, 1%
i.MX6Q - PCIe
+3.3V
2
2
R23X
68k, 1%
R15X
U100_9
iMX6Q - MCIMX6Q5EYM12AC
MPCIE_3.3V
J10X
1
2
2
C20X
S
1
1
2
100k, 1%
+3.3V
1
2
B
C19X
+GND
1
MPCIE_3.3V_4
49.9, 1%
+GND
GND_248
1
2
R13X
+GND
GND_239
+GND
2
P3.3V_DELAYED_57
GND_245
+VDD
R11X
68k, 1%
GND_247
R12X
C12X
PCIE_CLKREQ_N
VDDSOC_CAP_3
PCIE_PWRON
2
1
2
+GND
1.0uF, 25V, 20% X5R
0.1uF, 6.3V, X5R
1
+1.5V
C11X
GND_249
2
4.7uF, 10V, X5R, 10%
G
P1.5V_VGEN2_3
Q10X
2N7002W
1
2
C
8
330, 1%
GND_244
+GND
+GND
Mini PCI-express connector (TE 1717831 or Molex 679101002, 679100002, 0483380070)
P3.3V_DELAYED_58
2
2
+3.3V
D
R22X
10k, 1%
1
1
2
R21X
10k, 1%
1
1
2
D
SMB_SCL
SMB_SDA
Wifi plug-in card symbol placeholders
NT10X
DNXA-125 or DNXA-95 PCIe half-sized card, unex.com.tw
NT11X
Use ath9k-compatible PCIe card
Suggestions at left are for b/g/n 1x1 low-cost solution
Other options exist for a/b/g/n 2x2, 3x3 MIMO + BT combo
(note BT combo is via mPCIe embedded USB interface)
U.FL 2.5GHz antenna
NT12X
E
E
U.FL 2.5GHz antenna
Copyright 2014 Andrew "bunnie" Huang
Sheet: /U_12mPCIe/
File: 12mPCIe.sch
Novena
Title: 12mPCIe
1
2
3
4
Copyrights:
CC-BY-SA 3.0
5
Patents: Apache
2.0
6
PVT2-A
Size: B
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
7
Rev:
Id: 12/16
8
1
2
3
4
5
6
7
8
9
10
11
LCD interface
A
U100_11
iMX6Q - MCIMX6Q5EYM12AC
LVDS0_TX_2_N DIFFPAIR
LVDS0_TX_2_P DIFFPAIR
LVDS0_CLK_N
LVDS0_CLK_P
V4
V3
LVDS0_CLK_N DIFFPAIR
LVDS0_CLK_P DIFFPAIR
LVDS0_TX3_N
LVDS0_TX3_P
W2
W1
LVDS0_TX_3_N DIFFPAIR
LVDS0_TX_3_P DIFFPAIR
NVCC_LVDS2P5
LVDS1_TX2_N
LVDS1_TX2_P
DIFFPAIR
DIFFPAIR
LVDS1_CLK_N
LVDS1_CLK_P
Y3
Y4
LVDS1_CLK_N DIFFPAIR
LVDS1_CLK_P DIFFPAIR
LVDS1_TX3_N
LVDS1_TX3_P
AA3
AA4
LVDS1_TX_3_N DIFFPAIR
LVDS1_TX_3_P DIFFPAIR
Si4435DY
2
2
1.0uF, 25V, 20% X5R
C12L
GND_270
+GND
2
1
2
2
2
+GND
2
1
3
1
S
S
S
G
10k, 1%
2
Q12L
2N7002W
2
2
1
GND_266
R17L
49.9, 1%
1
P
backlight power
note: high (6-18V) voltage!
LCD_BL_VDD
Si4435DY
2
1
2
LCD_BL_VDD
+GND
C17L
C18L
GND_271
+GND
U10L
RT9706
1
3
2
1
1
1
GND_269
S
Q13L
2N7002W
3
G
1
2
GND_268
G
S
+GND
D
D
2
E
1
D
GND_264
1.0uF, 25V, 20% X5R
1
+GND
8
7
6
5
D
D
D
D
C19L
2
D
S
2
G
R18L
100k, 1%
+GND
1
2
3
4
R16L
2
1
USB_VID_P5V
USB_VID_N
USB_VID_P
R15L
10k, 1%
2
LCD_PWR_CTL
LCD_VCC_SW
C13L
BATT_PWR
1
R14L
6.04k, 1%
GND_263
combo logic+EDID power
voltage range compatible with most LED backlit displays
Q11L
1
1
R13L
6.04k, 1%
+GND
LVDS1_TX_3_N
LVDS1_TX_3_P
LCD_VCC_SW
DSI_REXT
GND_262
LVDS1_CLK_N
LVDS1_CLK_P
C
R19L
10k, 1%
R16L, R19L must divide BATT_PWR to protect Si4435DY 20V Vgs
Also means BATT_PWR > 6V to turn-on transistor
P5.0V_DELAYED_12
4
VIN
1
EN
+5V
USB_PWREN5_N
Q14L
2N7002W
2
GND_267
+GND
active pull-down in off state
to ensure LCD circuitry reset
2
VOUT
5
FLG
3
GND
C15L
GND_265
+GND
USB_VID_P5V
USB_OVERCUR5_N
P3.3V_DELAYED_60
+3.3V
C16L
54-pin FFC MOLEX 51296-5494 or equiv
G4
LVDS1_TX2_N
LVDS1_TX2_P
2
P
8
7
6
5
C14L
1
DSI_REXT
LVDS1_TX2_N
LVDS1_TX2_P
AB1
AB2
LVDS1_TX1_N
LVDS1_TX1_P
2
100k, 1%
1
CSI_REXT
DIFFPAIR
DIFFPAIR
1
1
1
CSI_REXT D4
LVDS1_TX1_N
LVDS1_TX1_P
1.0uF, 25V, 20% X5R
NVCC_MIPI
D
AA2
AA1
1
1
2
CSI_D3M
CSI_D3P
LVDS1_TX1_N
LVDS1_TX1_P
LVDS1_TX0_N
LVDS1_TX0_P
1
R11L
2
F2
F1
DIFFPAIR
DIFFPAIR
B
1
DSI_D1M
DSI_D1P
H2
H1
+3.3V
D
D
D
D
1
G2
G1
S
S
S
G
2
DSI_D0M
DSI_D0P
LVDS1_TX0_N
LVDS1_TX0_P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
2
1
2
3
4
22uF, 25V, X5R, 10%
CSI_D2M
CSI_D2P
Y1
Y2
LCD_VCC leads LCD_BL voltages in power-on and down transitions
Q10L
1
E1
E2
LVDS1_TX0_N
LVDS1_TX0_P
1
H3
H4
1
DSI_CLK0M
DSI_CLK0P
LVDS0_TX_3_N
LVDS0_TX_3_P
2
CSI_D1M
CSI_D1P
LVDS0_CLK_N
LVDS0_CLK_P
C11L
2
D1
D2
LVDS0_TX_2_N
LVDS0_TX_2_P
+VDD
+GND
0.1uF, 25V, X5R
CSI_D0M
CSI_D0P
NVCC_LVDS2P5
1
E4
E3
LVDS0_TX_1_N
LVDS0_TX_1_P
VDD_HIGH_CAP_6
GND_261
1
CSI_CLK0M
CSI_CLK0P
NVCC_MIPI
F4
F3
V7
LVDS0_TX_0_N
LVDS0_TX_0_P
2
ECSPI3_SCLK
ECSPI3_MOSI
ECSPI3_MISO
ECSPI3_SS0
HUB RST normally DNP, so available to talk to FPGA
ECSPI3_SS1
ECSPI3_SS2
USB_HUB2_RST AUD6_RXC
ECSPI3_RDY
GPIO_PWM1
GPIO_PWM2
FPGA_SUSPEND
FPGA_INIT_N
FPGA_DONE
FPGA_RESET_N
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
ACCEL_INT
TS_TOUCHED
PCIE_CLKREQ_N
AUD_HP_IN
PMIC_INT_B
AUD_PWRON
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
E
R12L
10k, 1%
2
P24
P22
P23
P21
P20
R25
R23
R24
R22
T25
R21
T23
T24
R20
U25
T22
T21
U24
V25
U23
U22
T20
V24
W24
P3.3V_DELAYED_61
1
V2
V1
1
DISP0_DAT0
DISP0_DAT1
DISP0_DAT2
DISP0_DAT3
DISP0_DAT4
DISP0_DAT5
DISP0_DAT6
DISP0_DAT7
DISP0_DAT8
DISP0_DAT9
DISP0_DAT10
DISP0_DAT11
DISP0_DAT12
DISP0_DAT13
DISP0_DAT14
DISP0_DAT15
DISP0_DAT16
DISP0_DAT17
DISP0_DAT18
DISP0_DAT19
DISP0_DAT20
DISP0_DAT21
DISP0_DAT22
DISP0_DAT23
2
CSI0_DAT4
CSI0_DAT5
CSI0_DAT6
CSI0_DAT7
CSI0_DAT8
CSI0_DAT9
CSI0_DAT10
CSI0_DAT11
CSI0_DAT12
CSI0_DAT13
CSI0_DAT14
CSI0_DAT15
CSI0_DAT16
CSI0_DAT17
CSI0_DAT18
CSI0_DAT19
AUD6_RXD
1
N1
P2
N4
N3
N6
N5
M1
M3
M2
L1
M4
M5
L4
L3
M6
L6
C
2
LVDS0_TX2_N
LVDS0_TX2_P
2
UART4_RTS
UART4_CTS
CSI0_VSYNC
CSI0_DATA_EN
1
1
N2
P3
2
1
2
LVDS0_TX_1_N DIFFPAIR
LVDS0_TX_1_P DIFFPAIR
JP10L
LCD_XP
LCD_YP
LCD_XM
LCD_YM
GPIO_PWM1
LCD_BL_ON
I2C3_SCL
I2C3_SDA
2
AUD_CLK_T
AUD_DOUT
B
49.9, 1%
AUD_LRCLK
AUD_DIN
These are alt pins used only on S/DL
SMB_SDA
SMB_SCL
LCD_PWR_CTL
AUD_ALRCK
These are alt pins used only on S/DL
UART4_TXD
UART4_RXD
2
LVDS0_TX1_N
LVDS0_TX1_P
U4
U3
1
AUD6_TXD
AUD6_TFS
USB_HUB1_RST
AUD6_TXC
0.1uF, 6.3V, X5R
AUD_CLK
R10L
LVDS0_TX_0_N DIFFPAIR
LVDS0_TX_0_P DIFFPAIR
2
N25
N20
P25
N21
0.1uF, 6.3V, X5R
BATT_NRST
BATT_REFLASH_ALRT
test point (DNP)
U2
U1
2
DI0_PIN2
DI0_PIN3
DI0_PIN4
DI0_PIN15
NVCC_LVDS2P5
DI0_DISP_CLK
1
CSI0_MCLK
CSI0_PIXCLK
N19
1
NVCC_LCD
1
49.9, 1% (DNP)
LVDS0_TX0_N
LVDS0_TX0_P
i.MX6Q - DISP; CSI
P4
P1
NVCC_CSI
AUD_CLK
J11L
1
1
1
2
2
2
2
i.MX6 S/DL has AUD_MCLK on P4
R26L
AUD_MCLK_T_SDL
0.5A / contact
4x for LCD digital logic (2A max)
5x for BL (2.5A x Vbat watts)
i.MX6Q - LVDS
U100_10
iMX6Q - MCIMX6Q5EYM12AC
4.7uF, 10V, X5R, 10%
AUD_MCLK
AUD_CLK
Designed to work with LED backlight panels
Interleaved pixel option to support UXGA resolutions
Requires custom cable to adapt pinout to specific LCD
10uF, 10V, X5R, 20%
A
HDMI-A connector
RCLAMP0524P
IO2B
2
R20L
1.8k, 1%
R33L
4.7k, 1%
1
G
S
3
IO4B
1
DDC_SDA_HV
HDMI_HPD
G
Q15L
BSS138
+GND
P3.3V_13
HDMI_HPD_CPU
+3.3V
2
D11L
HDMI_CLKM
HDMI_CLKP
IO1B10
IO2B9
IO1A
IO1B
IO2A
IO2B
TX0_TMDS3_NPCB Rule
TX0_TMDS3_P
1
1 IO1A
2 IO2A
PCB Rule TX0_TMDS3_N
TX0_TMDS3_P
1
+5V
R21L
1.8k, 1%
1
HDMI_HPD_CPU
2
J5
J6
P5.0V_DELAYED_13
2
HDMI_VPH
TX0_TMDS2_NDIFFPAIR
TX0_TMDS1_PDIFFPAIR
HDMI_TX
HDMI_TX
TX0_TMDS1_NDIFFPAIR
TX0_TMDS0_PDIFFPAIR
HDMI_TX
HDMI_TX
TX0_TMDS0_NDIFFPAIR
TX0_TMDS3_PDIFFPAIR
HDMI_TX
TX0_TMDS3_NDIFFPAIR
CEC R31L
3
4
6
7
8
GND_274
RCLAMP0524P
M7
C10L
0.1uF,
6.3V, X5R
+GND
1
HDMI_VP
2
L7
HDMI_TX
HDMI_TX
1
5
GND_275
2
K2
IO4A
TX0_TMDS2_PDIFFPAIR
R22L
1.8k, 1%
9
10
11
2
HDMI_DDCCEC
+GND
IO3B
1
K1
IO3B7
IO4B6
1
HDMI_HPD
4 IO3A
5 IO4A
IO3A
GND_255
HDMI_TX
F
J10L
2
Use P3.3V for P/Us because DDC lines are shared with PMIC lines
(why this is recommended by Freescale, I don't know)
2
DDC_SCL
DDC_SDA_HV
HDMI_HPD
i.MX6Q - HDMI
D
C21L
GND1
S
1
1
2
C20L
3 GND1
Q19L
BSS138
2
+GND
U100_12
iMX6Q - MCIMX6Q5EYM12AC
2
GND_258
0.1uF, 6.3V, X5R
1
1
+VDD
2
VDDSOC_CAP_4
2
4.7uF, 10V, X5R, 10%
2
IO2A
CEC
DDC_SCL_HV
2
IO1B
1
IO1B10
IO2B9
IO1A
2
1 IO1A
2 IO2A
CEC
DDC_SCL_HV
3
1
1
F
Matched Net Lengths [Tolerance = 2mil]
1
+3.3V
PCB Rule
P3.3V_14
D10L
D
HDMI ESD
Note leakage point on 3.3V line
(but, buffer prevents trivial attack on PMIC from HDMI port)
12
2
1
2
Matched Net Lengths [Tolerance = 40mil]
3 GND1
Matched Net Lengths [Tolerance = 2mil]
100, 1%
1
1
IO2B
P3.3V_DELAYED_63
P3.3V_DELAYED_62
+3.3V
+3.3V
IO3B
IO4B
TX0_TMDS2_N
TX0_TMDS2_PPCB Rule
HDMI_HPD_LV
19
1
1
0
GND_256
+GND
AUK HDM19SW-4-L2-1R3HHCN
1
2
GND_252
+GND
F10L
P5.0V_DELAYED_11
+5V
G
GND_273
GND_272
1
Q18L
2N7002W
1
1
2
2
D13L
RSA5M
HDMI_HPD
0ZCA0005FF2E
GND_257
+GND
INFO: 50MA hold
150MA TRIP
2
S
Q17L
2N7002W
2
RUN TRACES STRAIGHT UNDER ESD WITHOUT VIAS
1
S
G
LAYOUT: PLACE ESD IN SERIES TO ELIMINATE STUBS
HDMI +5V fuse
R30L
10k, 1%
HDMI_HPD_LV_N
D
Matched Net Lengths [Tolerance = 40mil]
H
1
2
330, 1%
R25L
47k, 1%
3
IO3B7
IO4B6
3
IO4A
R32L
2
2
2
IO3A
R29L
1k, 1%
2
4 IO3A
5 IO4A
HDMI_HPD
G
A
TX0_TMDS1_N
TX0_TMDS1_P
18
B
IO1B
GND1
GND_253
TX_HDMI_5V
2
IO1B10
IO2B9
3 GND1
TX0_TMDS2_N
TX0_TMDS2_P +GND
3
D
1
IO2A
S
K
IO1A
16
A
1 IO1A
2 IO2A
TX0_TMDS1_N
TX0_TMDS1_P
2
Q16L
BSS138
can't use 2N7002 here b/c Vth is too high
RCLAMP0524P
15
17
DDC_SDA
D12L
K3
K4
R23L
1.8k, 1%
G
1
2
1
2
1
2
R28L
0 ohm (DNP)
2
J3
J4
R27L
2
IO4B
1
1
IO4A
TX0_TMDS0_N
TX0_TMDS0_P
1
1.6k, 1%
+GND
IO3B
14
2
GND_260
IO3B7
IO4B6
IO3A
DDC_SCL_HV
DDC_SDA_HV
1
HDMI_D2M
HDMI_D2P
4 IO3A
5 IO4A
D
1
2
2
HDMI_D1M
HDMI_D1P
R24L
GND_254
0 ohm
HDMI_REF
TX0_TMDS0_N
TX0_TMDS0_P +GND
1
HDMI_REF
J1
C23L
K5
K6
2
1
1
2
C22L
HDMI_D0M
HDMI_D0P
1
+GND
2
GND_259
0.1uF, 6.3V, X5R
1
1
+VDD
2
G
2
4.7uF, 10V, X5R, 10%
GND1
VDD_HIGH_CAP_5
13
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GND
+GND
+GND
No HPD polarity select in software
So, hardware buffering required
LAYOUT: ROUTE HDMI_TX* AND TX* SHORT, STRAIGHT,
H
AND WITHOUT VIAS. ROUTE PAIRS WITH
100 OHM DIFFERENTIAL IMPEDANCE.
Copyright 2014 Andrew "bunnie" Huang
Sheet: /U_13hdmi_lcd/
File: 13hdmi_lcd.sch
Novena PVT2-A
Title: 13hdmi_lcd
Copyrights: CC-BY-SA 3.0
1
2
3
4
5
6
7
8
Size: C
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
Patents: Apache 2.0
9
10
Rev:
Id: 13/16
11
4
5
+3.3V
2
2
1
1
2
1
1
R28A
KEY_ROW1
R10A
1
2
1
2
1
2
2
0 ohm
1
20k, 1%
P5.0V_DELAYED_15
P10A
2
1
2
1
2
2
JST B2B-EH-A
1
+GND
C18A
1.0uF, 25V, 20% X5R
2
2
B
1
GND_288
1
2
2
+GND
C19A
1.0uF, 25V, 20% X5R
R33A
100k, 1%
1
GND_299
1
+GND
AUD_P3.3V_6
+3.3V
1
2
R13A
2
1
2
1
20k, 1%
P5.0V_DELAYED_14
P11A
+5V
SPK_R_P
SPK_R_N
U12A
1
2
3
4
R14A
CN_L_SPK_LINE
2
1
1
VO2
GND
VDD
VO1
20k, 1%
1
2
1
C
C27A
1.0uF, 25V, 20% X5R
2
1
+GND
NSIWAY NS4890B
2
JST B2B-EH-A
GND_291
1
2
SHDWN
BYP
+IN
-IN
8
7
6
5
2
0.1uF, 6.3V, X5R
1
C22A
2
C25A
2
+GND
1
2
1
GND_278
10uF, 10V, X5R, 20%
2
2
Note: TS4990IST can be substituted for NS4890
C23A
2
CN_R_SPK_LINE
2
GND_290
+GND
1
2
1
HP_R_PRE
HP_L_PRE
2
C29A
1.0uF, 25V, 20% X5R
10uF, 10V, X5R, 20%
AUD_P3.3V_7
+3.3V
2
1
R32A
100, 1% (DNP)
8
7
6
5
NSIWAY NS4890B
10uF, 10V, X5R, 20%
1
VO2
GND
VDD
VO1
GND_289
20k, 1%
C28A
1
SHDWN
BYP
+IN
-IN
1
1
2
1
1
2
3
4
2
10uF, 10V, X5R, 20%
0.1uF, 6.3V, X5R
+GND
1
2
1
C17A
GND_281
1
2
R29A
100, 1% (DNP)
2
1
2
2
1
0.1uF, 6.3V, X5R
C16A
1
+GND
AUD_PA_SHDN
2
1
R12A
2
2
2
1
GND_283
1
SPK_L_P
SPK_L_N
U10A
R30A
2
1.0uF, 25V, 20% X5R
2
+GND
+GND
C24A
+GND
1
1
A
AUD_P3.3V_8
R25A
2
+3.3V
GND_280
AUD_DIN
AUD_ALRCK
AUD_MCLK
2
+1.8V
C13A
GND_282
GND_279
1
1
2
0 ohm (DNP)
AUD_P3.3V_5
C26A
+GND
1
2
2
1
1
1
1
2
AUD_VMID
AUD_VREF
1
GND_298
note: reprogram in BSP to 3.0V for micbias use, in case AUD_P3.3V is too noisy
P1.8V_VGEN3_2
2
1
0 ohm (DNP)
2
2
2
1
21
20
19
18
17
16
15
RIN2
VMID
ADCVREF
AGND
AVDD
HPVDD
LOUT2
1
MCLK
DVDD
PVDD
DGND
SCLK
DSDIN
DLRCK
PAD
CCLK
CDATA
CE
DACREF
LIN1
RIN1
LIN2
1
2
3
4
AUD_CLK
5
AUD_DOUT 6
AUD_LRCLK 7
P3.3V_DELAYED_66
+3.3V
R24A
1
AUD_PWRON
U11A
Everest ES8328E
0.1uF, 6.3V, X5R
+GND
C36A
0 ohm
8
9
10
11
12
13
14
2200pF, X7R, 50V, 10%
GND_297
1.0uF, 25V, 20% X5R
0.1uF, 6.3V, X5R
29
28
27
26
25
24
23
22
C41A
ASDOUT
ALRCK
OUT3
ROUT1
LOUT1
HPGND
ROUT2
1
2200pF, X7R, 50V, 10%
2
1
2
C21A
1
2
2
1
C20A
0.1uF, 6.3V, X5R
1
1.0uF, 25V, 20% X5R
+GND
1
2
1
1
0.1uF, 6.3V, X5R
MIC_DIFF_N DIFFPAIR
1
1
2
2
2
2
1
1
0.1uF, 6.3V, X5R
GND_277
+3.3V
2
2
2
R11A
10k,MIC_DIFF_P
1%
DIFFPAIR
AUD_I2C3_SCL
AUD_MCLK
AUD_P3.3V_3
2
1
1k, 1%
2
1
AUD_I2C3_SDA
2
C
C40A
1
1
C15A
1
2
C14A
B
8
+5V
2
+GND
C39A
+3.3V
1
2
2
GND_284
C38A
AUD_P3.3V_4
1
0.1uF, 6.3V, X5R
+3.3V
+GND
C12A
1
AUD_P3.3V_2
7
R23A
1
1
1
2
6
1
HP_VGND_EMI
2
2
330, 1%
GND_276
C37A
2
R27A
I2C3_SDA
C11A
C35A
10uF, 10V, X5R, 20%
2
2
1
C10A
2
2
1
1
+GND
MIC_CABLE
2
330, 1%
GND_287
2
0.1uF, 6.3V, X5R
1
2
1
2.2k, 1%
2
1
2
1
2
1k, 1%
R26A
I2C3_SCL
R11B
1k, 1%
1
1
2
R10B
1
2
2
+3.3V
10uF, 10V, X5R, 20%
P3.3V_DELAYED_65
A
1
1
0.01uF, 10V, X5R, 10%
R22A
Microphone configured for pseudo-differential operation
2
3
2
2
10uF, 10V, X5R, 20%
1
1
2
L10A
1
2
1
1
2
2
1
2
1
BLM18KG121
R15A
100k, 1%
MIC_CABLE
3A 120 ohm
4 J12A
5
3
2
1
S
R
HPR_EMI
R16A
AUD_HP_IN
2
1
47k, 1%
2
1
2
2
D
1
G
1
Q10A
2N7002W
2
+GND
S
1
L13A
2
1
2
1
2
+GND
BLM18KG121
3A 120 ohm (DNP)
2
GND_293
1
1
GND_286
+GND
1
2
1
2
HP_VGND_EMI
BLM18KG121
2
2
CUI SJ-43515TS-SMT
R18A
10k, 1%
GND_295
3A 120 ohm
L12A
AUD_PWRON
R19A
68k, 1%
+GND
GND_292
R20A
2
2
1
0.1uF, 6.3V, X5R
2
1
3
10k, 1%
1
2
BLM18KG121
1
2
2
1
T
2
1
D
TN
HPL_EMI
L11A
1
R17A
1
C32A
R
HP_IN
1
2
1
Power management switch for audio circuit
D
1
AUD_P3.3V
+3.3V
P3.3V_DELAYED_64
2
S
D
D11A
D12A
1
1
1
1
D10A
D13A
D14A
3
D
1
A
ESD5Z3.3T1
2
A
A
A
ESD5Z3.3T1
2
E
S
G
Q12A
2N7002W
+GND
ESD5Z3.3T1
2
3
E
GND_285
ESD5Z3.3T1
2
0.1uF, 25V, X5R
R21A
20 ohms, 1%
2
2
1
Q11A
FDN304P
ESD5Z3.3T1
2
A
1
+3.3V
K
K
1
3A 120 ohm
K
C34A
G
+GND
K
1
GND_296
K
2
1
2
100k, 1%
2
GND_294
+GND
Copyright 2014 Andrew "bunnie" Huang
active pulldown
to ensure audio codec reset
Sheet: /U_14audio/
File: 14audio.sch
Novena
Title: 14audio
1
2
3
4
Copyrights:
CC-BY-SA 3.0
5
Patents: Apache
2.0
6
PVT2-A
Size: B
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
7
Rev:
Id: 14/16
8
1
2
1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
P9
R12
R6
U14
U4
U9
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
E2
G4
J2
J5
M4
R2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
B1
B17
E14
E5
E9
G10
J12
K7
M9
P10
P14
P5
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
G7
H11
H9
J10
J8
K11
K9
L10
L8
M12
M7
P1.2V
+1.2V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
1
2
K10
K8
L11
L9
M17
M2
M6
N13
R1
R14
R18
R4
R9
T16
U12
U6
V1
V18
B
GND_301
+GND
GND_300
+GND
XC6SLX45-3CSG324C
P3.3V_DELAYED_72
+3.3V
R22F
1
2
1
2
4.7k, 1%
P3.3V_DELAYED_73
1
2
2
+3.3V
R25F
4.7k, 1%
U800_5
FPGA_DONE
V17
DONE_2
P3.3V_DELAYED_74
FPGA_RESET_N V2 PROGRAM_B_2
FPGA_SUSPEND
R16 SUSPEND
+3.3V
P10F
1
2
3
4
5
6
D
1
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
2
3
4
5
A17
D15
D16
B18
TCK
TDI
TDO
TMS
P13
CMPCS_B_2
2
6
R23F
10k, 1%
+GND
2
1
2
2
U15
V15
M11
N11
T12
V12
N10
P11
M10
N9
M8
N8
N7
P8
N6
P7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
1
22uF, 6.3V, X5R, 20%
C63F
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
label pins on silk
F7
E6
E7
E8
G8
F8
G11
F10
F11
E11
D12
C12
C13
A13
F12
E12
Male 2.54mm
+GND 6x1 header
GND_302
1
1
XC6SLX45-3CSG324C
1
1
2
2
R11F
1k, 1% (DNP)
U800_4
FDDR_D
FDDR_D
FDDR_D
FDDR_D
FDDR_D
FDDR_D
FDDR_D
FDDR_D
FDDR_DH
FDDR_DH
FDDR_DH
FDDR_DH
FDDR_DH
FDDR_DH
FDDR_DH
FDDR_DH
M8 VREFCA
H1 VREFDQ
1
+1.5V
+1.5V
LDQS F3
LDQS# G3
F_LDQS_P
F_LDQS_N
DIFFPAIR
DIFFPAIR
UDQS C7
UDQS# B7
F_UDQS_P
F_UDQS_N
DIFFPAIR
DIFFPAIR
F_LDM
F_UDM
FDDR_D
FDDR_DH
LDM E7
UDM D3
WE#
CAS#
RAS#
CS#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B1
B9
D1
D8
E2
E8
F9
G1
G9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
GND_320
+GND
MT41J128M16JT-125:K
F_DDR3_RST_N
FDDR_C
2
RESET# T2
ZQ L8
F_DDR3_ZQ
R33F
4.7k, 1%
+GND
2
K1 ODT
1
GND_324
1
2
R34F
240, 1%
+GND
MT41J128M16JT-125:K
1
1
2
C81F
2
C80F
0.1uF, 6.3V, X5R
1
1
2
2
C79F
0.1uF, 6.3V, X5R
1
1
2
1
2
2
C78F
2
0.1uF, 6.3V, X5R
1
0.1uF, 6.3V, X5R
1
2
1
C77F
2
0.1uF, 6.3V, X5R
1
2
1
C76F
2
0.1uF, 6.3V, X5R
1
2
1
C74F
2
2
1
C73F
2
2
1
C72F
0.1uF, 6.3V, X5R
1
1
0.1uF, 6.3V, X5R
1
1
GND_323
2
0.1uF, 6.3V, X5R
1
1
2
GND_321
2
2
P1.5V_DDR_SW3_13
10uF, 10V, X5R, 20%
GND_325
B2
D9
G7
K2
K8
N1
N9
R1
R9
P1.5V_DDR_SW3_10
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
2
J7 CK
K7 CK#
K9 CKE
A1
A8
C1
C9
D2
E9
F1
H2
H9
P1.5V_DDR_SW3_9
DDC_SCL
DDC_SDA
RESETBMCU
AUD_MCLK
FPGA_LSPI_MISO
FPGA_LSPI_CS
F_DX18
FPGA_LSPI_CLK
FPGA_LSPI_MOSI
FPGA_LSPI_WP
2
1
1
Copyright 2014 Andrew "bunnie" Huang
Sheet: /U_15fpga/
File: 15fpga.sch
Copyrights: CC-BY-SA 3.0
3
4
5
6
7
8
Size: C
Patents: ApacheKiCad
2.0 E.D.A.
Novena PVT2-A
9
Date: 22 12 2014
eeschema (2014-08-05 BZR 5054)-product
10
GND_319
FPGA_LSPI_HOLD
C91F
2
0.1uF, 6.3V, X5R
1
1
2
C90F
2
C89F
0.1uF, 6.3V, X5R
1
1
2
2
C88F
0.1uF, 6.3V, X5R
1
1
2
2
C87F
0.1uF, 6.3V, X5R
1
1
2
2
C86F
0.1uF, 6.3V, X5R
1
1
2
2
C85F
0.1uF, 6.3V, X5R
1
1
2
C84F
+GND
2
+1.5V
GND_329
F
R24F
10k, 1%
+GND
G
XC6SLX45-3CSG324C
P1.5V_DDR_SW3_14
E
1
F_DDR3_D0
F_DDR3_D1
F_DDR3_D2
F_DDR3_D3
F_DDR3_D4
F_DDR3_D5
F_DDR3_D6
F_DDR3_D7
F_DDR3_D8
F_DDR3_D9
F_DDR3_D10
F_DDR3_D11
F_DDR3_D12
F_DDR3_D13
F_DDR3_D14
F_DDR3_D15
1
1
M2 BA0
N8 BA1
M3 BA2
L3
K3
J3
L2
BANK 3
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
SMB_SDA
SMB_SCL
I2C3_SCL
I2C3_SDA
F_DX16
F_DX15
UART4_RTS
UART4_CTS
F_DX14
UART4_RXD
F_DX13
UART4_TXD
BATT_REFLASH_ALRT
BATT_NRST
F_DX12
F_DX11
F_LVDSC_P
DIFFPAIR
F_LVDSC_N
DIFFPAIR
F_DX8
APOPTOSIS
F_DX7
F_DX6
F_DX5
F_DX4
CLK2_P
CLK2_N
F_LVDSA_P
DIFFPAIR
F_LVDSA_N
DIFFPAIR
F_LVDSB_P
DIFFPAIR
F_LVDSB_N
DIFFPAIR
F_DX3
F_DX2
F_DX1
F_DX0
USB_HUB2_RST
F_DX17
1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
2
2
U12F_2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
N4
N3
P4
P3
L6
M5
U2
U1
T2
T1
P2
P1
N2
N1
M3
M1
L2
L1
K2
K1
L4
L3
J3
J1
H2
H1
K4
K3
L5
K5
H4
H3
L7
K6
G3
G1
J7
J6
F2
F1
H6
H5
E3
E1
F4
F3
D2
D1
H7
G6
E4
D3
F6
F5
C2
C1
2
1
FDDR3_VREF
U12F
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
IO_L1P_3
IO_L1N_VREF_3
IO_L2P_3
IO_L2N_3
IO_L31P_3
IO_L31N_VREF_3
IO_L32P_M3DQ14_3
IO_L32N_M3DQ15_3
IO_L33P_M3DQ12_3
IO_L33N_M3DQ13_3
IO_L34P_M3UDQS_3
IO_L34N_M3UDQSN_3
IO_L35P_M3DQ10_3
IO_L35N_M3DQ11_3
IO_L36P_M3DQ8_3
IO_L36N_M3DQ9_3
IO_L37P_M3DQ0_3
IO_L37N_M3DQ1_3
IO_L38P_M3DQ2_3
IO_L38N_M3DQ3_3
IO_L39P_M3LDQS_3
IO_L39N_M3LDQSN_3
IO_L40P_M3DQ6_3
IO_L40N_M3DQ7_3
IO_L41P_GCLK27_M3DQ4_3
IO_L41N_GCLK26_M3DQ5_3
IO_L42P_GCLK25_TRDY2_M3UDM_3
IO_L42N_GCLK24_M3LDM_3
IO_L43P_GCLK23_M3RASN_3
IO_L43N_GCLK22_IRDY2_M3CASN_3
IO_L44P_GCLK21_M3A5_3
IO_L44N_GCLK20_M3A6_3
IO_L45P_M3A3_3
IO_L45N_M3ODT_3
IO_L46P_M3CLK_3
IO_L46N_M3CLKN_3
IO_L47P_M3A0_3
IO_L47N_M3A1_3
IO_L48P_M3BA0_3
IO_L48N_M3BA1_3
IO_L49P_M3A7_3
IO_L49N_M3A2_3
IO_L50P_M3WE_3
IO_L50N_M3BA2_3
IO_L51P_M3A10_3
IO_L51N_M3A4_3
IO_L52P_M3A8_3
IO_L52N_M3A9_3
IO_L53P_M3CKE_3
IO_L53N_M3A12_3
IO_L54P_M3RESET_3
IO_L54N_M3A11_3
IO_L55P_M3A13_3
IO_L55N_M3A14_3
IO_L83P_3
IO_L83N_VREF_3
2
2
R29F
1k, 1% (DNP)
2
1
1
2
1
C69F
2
+GND
0.1uF, 6.3V, X5R
1
1
2
1
C68F
GND_322
2
2
1
1
1
GND_326
C67F
FDDR3_VREF
0.1uF, 6.3V, X5R
2
F_DDR3_RZQ
FDDR3_VREF
R28F
F_DDR3_A13
100, 1%
UIM_PWR
+GND
F_DDR3_RST_N
F_DDR3_A11
FDDR_CF_DDR3_A0
F_DDR3_CKE
FDDR_CF_DDR3_A1
F_DDR3_A12
FDDR_CF_DDR3_A2
F_DDR3_A8
FDDR_CF_DDR3_A3
F_DDR3_A9
FDDR_CF_DDR3_A4
F_DDR3_A10
FDDR_CF_DDR3_A5
F_DDR3_A4
FDDR_CF_DDR3_A6
F_WE_N
FDDR_CF_DDR3_A7
F_BA2
FDDR_CF_DDR3_A8
F_DDR3_A7
FDDR_CF_DDR3_A9
F_DDR3_A2
FDDR_CF_DDR3_A10
F_BA0
FDDR_CF_DDR3_A11
F_BA1
FDDR_CF_DDR3_A12
F_DDR3_A0
FDDR_CF_DDR3_A13
F_DDR3_A1
R31F
F_DDR3_CK_P
100, 1% (DNP)
F_DDR3_CK_N
F_DDR3_A3
FDDR_CF_BA0
F_DDR3_ODT
FDDR_CF_BA1
F_DDR3_A5
FDDR_CF_BA2
F_DDR3_A6
F_RAS_N
DIFFPAIR F_DDR3_CK_P
F_CAS_N
DIFFPAIR F_DDR3_CK_N
F_UDM
FDDR_C
F_DDR3_CKE
F_LDM
R32F
F_DDR3_D4
4.7k, 1%
F_DDR3_D5
FDDR_C
F_WE_N
F_DDR3_D6
FDDR_C F_CAS_N
F_DDR3_D7
FDDR_C F_RAS_N
+GND
F_LDQS_P
F_LDQS_N
F_DDR3_D2
F_DDR3_D3
FDDR_CF_DDR3_ODT
F_DDR3_D0
F_DDR3_D1
F_DDR3_D8
F_DDR3_D9
F_DDR3_D10
F_DDR3_D11
F_UDQS_P
F_UDQS_N
F_DDR3_D12
F_DDR3_D13
+1.5V
F_DDR3_D14
C71F
C70F
F_DDR3_D15
+GND
F_DDR3_ZIO
FDDR3_VREF
2
C94F
1.0uF, 25V, 20% X5R
2
2
1
C93F
1
2
1
0.1uF, 6.3V, X5R
2
1
C92F
2
0.1uF, 6.3V, X5R
UIM_PWR is open-drain pulldown
1
+GND
2
GND_330
+1.5V
Title: 15fpga
2
A
P1.5V_DDR_SW3_15
2
10uF, 10V, X5R, 20%
2
0 ohm, 0805
XC6SLX45-3CSG324C
1
C31F
2
2
1
1
U800_7
A1
A18
B13
B7
C16
C3
D10
D5
E15
G12
G17
G2
G5
H10
H8
J11
J15
J4
J9
C30F
1.0uF, 25V, 20% X5R
E17
G15
J14
J17
M15
R17
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
10uF, 10V, X5R, 20%
2
1
1
2
2
1
2
2
1
2
2
0.1uF, 6.3V, X5R
1
0.1uF, 6.3V, X5R
1
0.1uF, 6.3V, X5R
1
1
2
2
1
2
2
1
2
2
0.1uF, 6.3V, X5R
1
0.1uF, 6.3V, X5R
1
0.1uF, 6.3V, X5R
1
1
2
2
2
1
1
1.0uF, 25V, 20% X5R
1
2
2
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
1
10uF, 10V, X5R, 20%
2
1
1
B10
B15
B5
D13
D7
E10
2
2
1.0uF, 25V, 20% X5R
1
1
2
2
1
1
2
2
K
+0.75V
F15
F16
C17
C18
F14
G14
D17
D18
H12
G13
E16
E18
K12
K13
F17
F18
H13
H14
H15
H16
G16
G18
J13
K14
L12
L13
K15
K16
L15
L16
H17
H18
J16
J18
K17
K18
L17
L18
M16
M18
N17
N18
P17
P18
N15
N16
T17
T18
U17
U18
M14
N14
L14
M13
P15
P16
C29F
U800_8
2
1
100k, 1%
2N7002W
1
2
1
1
2
2
1
10uF, 10V, X5R, 20%
2
1
1
1
1.0uF, 25V, 20% X5R
10uF, 10V, X5R, 20%
2
2
1
1
1
2
2
0.1uF, 6.3V, X5R
1
2
2
2
1
1
2
2
1
2
2
1
0.1uF, 6.3V, X5R
1
1
1
2
2
0.1uF, 6.3V, X5R
1
0.1uF, 6.3V, X5R
1
1
2
2
1
2
2
1
2
2
0.1uF, 6.3V, X5R
1
2
2
1
0.1uF, 6.3V, X5R
1
1
1
2
2
1
1
1
2
2
0.1uF, 6.3V, X5R
1
2
0.1uF, 6.3V, X5R
2
1
2
2
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
1
0.1uF, 6.3V, X5R
1
0.1uF, 6.3V, X5R
1
2
2
1
2
2
0.1uF, 6.3V, X5R
1
2
2
1
2
2
1
2
2
1
1
1
1
1
2
0.1uF, 6.3V, X5R
1
2
2
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
1
2
1
2
2
1
2
2
0.1uF, 6.3V, X5R
1
1
1
1
2
2
1
0.1uF, 6.3V, X5R
1
1
2
2
1
0.1uF, 6.3V, X5R
A
2
FPGA_EXP_ON
1
0.1uF, 6.3V, X5R
H
1
1
1
C62F
C28F
R10F
P0.75V_REFDDR_6
2
G
1
2
2
2
G
+GND
C27F
GND_303
S
1
R36F
10k, 1%
GND_315
C26F
P3.3V_DELAYED_70
XC6SLX45-3CSG324C
1
* WDOG_RST output from CPU is also provided
May be necessary to tie that to apoptosis
So a crash/watchdog reset forces apoptosis?
D11F
CDBMT220L-G or CDBMT240-HF
C25F
C
2
2.2uH, coilcraft MSS5131-222ML
C24F
XC6SLX45-3CSG324C
2
1
LMR10520YSDE
1
1
2
2
+GND
1
C23F
+3.3V
C61F
L10F
1
+3.3V
3
D
1
2
C50F
10uF, 10V, X5R, 20%
P3.3V_DELAYED_82
1
1
2
R35F
10k, 1%
BANK 1
1
A
K
2
GND_318
1
2
3
7
C65F
1
1
2
Q10F
2N7002W
1
10.5k, 1%
C22F
+GND
11
U800_6
+1.5V
C60F
+3.3V
GND_306
+3.3V
+3.3V
C59F
P3.3V_DELAYED_67
P3.3V_DELAYED_69
P1.5V_DDR_SW3_11
C49F
1
2
FB
GND
SW
GND
1
G
S
+GND
C58F
22uF, 6.3V, X5R, 20%
EN
VINA
VIND
1
1
GND_317
2
C21F
C41F
+1.2V
1
74AUP1T97GW
C57F
C48F
C20F
P3.3V_DELAYED_81
+GND
2
GND_316
C47F
C40F
P1.2V_3
2
RESETBMCU
C56F
C39F
U10F
Q12F
R30F
C19F
1.0uF, 25V, 20% X5R
2
1
R21F
4.7k, 1%
2
1
10k, 1%
0.1uF, 6.3V, X5R
1.0uF, 25V, 20% X5R
CPU_TAMPER
1
2
R20F
10k, 1%
2
2
C46F
2
2
1
0 ohm (DNP)
C55F
GND_304
+GND
1
R26F
1
R27F
330, 1%
+GND
P1.2V_2
+1.2V
1
FPGA_RESET_N
C45F
C38F
R19F
2
1
6
5
4
1
C
Vcc
Y
3
B
GND
A
D
1
2
3
2
+3.3V
U11F
D12F
2
1
1
P3.3V_DELAYED_79
2
2
C66F
2
Setting apoptosis creates a one-way 'trap', such that
the FPGA can only be configured once after boot
+3.3V
C54F
R18F
2
+5V
+3.3V
IO_L1P_A25_1
IO_L1N_A24_VREF_1
IO_L29P_A23_M1A13_1
IO_L29N_A22_M1A14_1
IO_L30P_A21_M1RESET_1
IO_L30N_A20_M1A11_1
IO_L31P_A19_M1CKE_1
IO_L31N_A18_M1A12_1
IO_L32P_A17_M1A8_1
IO_L32N_A16_M1A9_1
IO_L33P_A15_M1A10_1
IO_L33N_A14_M1A4_1
IO_L34P_A13_M1WE_1
IO_L34N_A12_M1BA2_1
IO_L35P_A11_M1A7_1
IO_L35N_A10_M1A2_1
IO_L36P_A9_M1BA0_1
IO_L36N_A8_M1BA1_1
IO_L37P_A7_M1A0_1
IO_L37N_A6_M1A1_1
IO_L38P_A5_M1CLK_1
IO_L38N_A4_M1CLKN_1
IO_L39P_M1A3_1
IO_L39N_M1ODT_1
IO_L40P_GCLK11_M1A5_1
IO_L40N_GCLK10_M1A6_1
IO_L41P_GCLK9_IRDY1_M1RASN_1
IO_L41N_GCLK8_M1CASN_1
IO_L42P_GCLK7_M1UDM_1
IO_L42N_GCLK6_TRDY1_M1LDM_1
IO_L43P_GCLK5_M1DQ4_1
IO_L43N_GCLK4_M1DQ5_1
IO_L44P_A3_M1DQ6_1
IO_L44N_A2_M1DQ7_1
IO_L45P_A1_M1LDQS_1
IO_L45N_A0_M1LDQSN_1
IO_L46P_FCS_B_M1DQ2_1
IO_L46N_FOE_B_M1DQ3_1
IO_L47P_FWE_B_M1DQ0_1
IO_L47N_LDC_M1DQ1_1
IO_L48P_HDC_M1DQ8_1
IO_L48N_M1DQ9_1
IO_L49P_M1DQ10_1
IO_L49N_M1DQ11_1
IO_L50P_M1UDQS_1
IO_L50N_M1UDQSN_1
IO_L51P_M1DQ12_1
IO_L51N_M1DQ13_1
IO_L52P_M1DQ14_1
IO_L52N_M1DQ15_1
IO_L53P_1
IO_L53N_VREF_1
IO_L61P_1
IO_L61N_1
IO_L74P_AWAKE_1
IO_L74N_DOUT_BUSY_1
FPGA_LED2
2
0.1uF, 6.3V, X5R
1
1
2
2
1
2
2
+GND
P5.0V_DELAYED_16
P3.3V_DELAYED_78
U800_2
1
P3.3V_DELAYED_80
APT1608SGC green
SN74AUP1T97 is configured as NOR-gate, B-input inverted
When apoptosis is high, resetting the FPGA resets the CPU
Apoptosis is normally pulled down, so if unconfigured,
apoptosis is effectively inactive
+GND
C37F
GND_314
Si4435DY
C83F
GND_310
C36F
GND_313
2
1.0uF, 25V, 20% X5R
10uF, 10V, X5R, 20%
1
0.1uF, 25V, X5R
2
1
2
F_LVDS2_N
F_LVDS2_P
F_LVDSA_P
F_LVDSA_N
F_LVDS1_P
F_LVDS1_N
F_LVDS4_P
F_LVDS4_N
F_DX14
F_LVDS_CK1_P
F_LVDS_CK1_N
F_LVDS0_P
F_LVDS0_N
F_LVDS15_P
F_LVDS15_N
F_LVDSB_N
F_LVDSB_P
F_DX17
F_LVDS11_P
F_LVDS11_N
F_DX1
F_LVDSC_N
F_LVDSC_P
TAMPER, !RESETBMCU
0.1uF, 6.3V, X5R
APOPTOSIS
+GND
C43F
C18F
1.23V enables extended MCB performance range
pin-compatible downgrade to LMR10510 / MSS5121 / CDBM140-G and half-value caps for 1A
+GND
2
1
Apoptosis function
FPGA_RESET_N
APOPTOSIS
F
C82F
GND_328
C35F
2
A40
A39
A38
A37
A36
GND4
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
GND3
A24
A23
A22
A21
A20
A19
A18
A17
A16
GND2
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
GND1
A5
A4
A3
A2
A1
+GND
F_DX0
F_DX3
F_DX2
F_DX11
DDC_SDA
GND_327
E
+3.3V
C53F
1
C52F
C34F
P3.3V_DELAYED_75
C42F
0.1uF, 6.3V, X5R
2
1
1
0.1uF, 6.3V, X5R
1
2
2
1
C51F
C33F
1.23V FPGA Vcore regulator - up to 2A
B40
B39
B38
B37
B36
GND8
F_DX15
F_DX7
F_DX12
F_DX6
F_DX13
F_LVDS7_P
F_LVDS7_N
B35
B34
B33
F_LVDS3_N
F_LVDS3_P
B32
B31
B30
B29
B28
F_LVDS5_P
F_LVDS5_N
F_LVDS6_N
F_LVDS6_P
B27
B26
B25
GND7
F_LVDS8_P
F_LVDS8_N
B24
B23
B22
B21
B20
F_LVDS9_P
F_LVDS9_N
F_LVDS_CK0_P
F_LVDS_CK0_N
B19
B18
B17
B16
GND6
F_DX18
F_LVDS10_P
F_LVDS10_N
B15
B14
B13
B12
B11
B10
F_LVDS13_P
F_LVDS13_N
F_DX16
F_LVDS12_P
F_LVDS12_N
B9
B8
F_DX8
B7
B6
B5
GND5
B4
B3
F_DX5
F_DX4
DDC_SCL
F_LVDS14_P
F_LVDS14_N
B2
B1
B1
B2
B3
B4
B5
GND5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
GND6
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
GND7
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
GND8
B36
B37
B38
B39
B40
A1
A2
A3
A4
A5
GND1
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
GND2
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
GND3
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
GND4
A36
A37
A38
A39
A40
1
P5.0V_FEXP
1
+GND
2
1
1
C32F
GND_309
0.1uF, 6.3V, X5R
4.7k, 1% (DNP)
+3.3V
2
2
P3.3V_DELAYED_71
2
2
1
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
1
GND_307
C95F
C17F
4.7k, 1%
6
5
4
+5V
P
C44F
C16F
2
R17F
GND_312
1
2
3
4
C15F
+GND
2
1
F_LVDS12_P
DIFFPAIR
+GND
F_LVDS12_N
DIFFPAIR
F_LVDS11_P
DIFFPAIR
F_LVDS11_N
DIFFPAIR
F_LVDS10_P
DIFFPAIR
F_LVDS10_N
DIFFPAIR
F_LVDS_CK1_P DIFFPAIR
F_LVDS_CK1_N DIFFPAIR
F_LVDS15_P
DIFFPAIR
F_LVDS15_N
DIFFPAIR
F_LVDS_CK0_P DIFFPAIR
F_LVDS_CK0_N DIFFPAIR
F_LVDS9_P DIFFPAIR
F_LVDS9_N DIFFPAIR
F_LVDS8_P DIFFPAIR
F_LVDS8_N DIFFPAIR
F_LVDS7_P DIFFPAIR
F_LVDS7_N DIFFPAIR
F_LVDS6_P
DIFFPAIR
F_LVDS6_N
DIFFPAIR
F_LVDS5_P
DIFFPAIR
F_LVDS5_N
DIFFPAIR
F_LVDS4_P
DIFFPAIR
F_LVDS4_N
DIFFPAIR
F_LVDS3_P
DIFFPAIR
F_LVDS3_N
DIFFPAIR
F_LVDS2_P
DIFFPAIR
F_LVDS2_N
DIFFPAIR
F_LVDS1_P
DIFFPAIR
F_LVDS1_N
DIFFPAIR
F_LVDS0_P
DIFFPAIR
F_LVDS0_N
DIFFPAIR
FPGA_INIT_N prog
S
S
S
G
+1.5V
GND_305
2
1
P5.0V_DELAYED_17
D
D
D
D
2
R16F
P1.5V_DDR_SW3_12
2
F_LVDS13_P DIFFPAIR
F_LVDS13_N DIFFPAIR
FPGA_M1 prog
Q11F
1
1
1
2
2
All power generation is local to expansion board
Connects to 2x AD9286 or ISLA118P50 500MSPS 8-bit ADCs
8 LVDS pairs + clock in; LVDS[A,B] for OR; LVDSC for clockout
SPI CLK,DIO,CS for config (use local inverter to generate 2x CS)
19 digital I/O total -- 3 for SPI leaves 16 for LA use
DDC_SDA/DDC_SCL for I2C config use
Badly matched F_DX*: F_DX14, F_DX17, F_DX18 - use for SPI
Rest are matched to within 500 mil
8
7
6
5
C14F
4.7k, 1% (DNP)
XC6SLX45-3CSG324C
JP10F
FX10A-80S/8-SV(**)
C13F
2
1
High speed expansion notes:
D
C12F
0.1uF, 6.3V, X5R
4.7k, 1%
R15F
1
C11F
0.1uF, 6.3V, X5R
2
C10F
+GND
0.1uF, 6.3V, X5R
2
1
0.1uF, 6.3V, X5R
1
+3.3V
GND_308
2
R14F
ECSPI3_SCLK prog+3.3V
FPGA_M0
F_LVDS14_P DIFFPAIR
F_LVDS14_N DIFFPAIR
ECSPI3_MOSI prog
P3.3V_DELAYED_68
2
XC6SLX45-3CSG324C
R15
T15
U16
V16
R13
T13
T14
V14
N12
P12
U13
V13
R11
T11
U11
V11
R10
T10
U10
V10
R8
T8
T9
V9
U8
V8
U7
V7
T6
V6
R7
T7
R5
T5
U5
V5
R3
T3
T4
V4
N5
P6
U3
V3
P3.3V_DELAYED_76
0.1uF, 6.3V, X5R
ECSPI3_SS2
ECSPI3_MISO
AUD6_TXC
AUD6_TFS
USB_HUB1_RST
ECSPI3_RDY
EIM_DA15
AUD6_TXD
EIM_DA12
EIM_WAIT
EIM_DA9
EIM_DA11
EIM_DA8
EIM_DA7
ECSPI3_SCLK
EIM_BCLK
EIM_DA3
EIM_DA6
EIM_DA10
EIM_DA13
EIM_OE
EIM_DA1
EIM_DA0
EIM_DA2
EIM_CS0
EIM_A16
EIM_A17
UIM_DATA
EIM_LBA
UIM_PWRON
EIM_DA5
EIM_DA4
UIM_RESET
EIM_CS1
EIM_A18
EIM_RW
UIM_CLK
FPGA_LED2
BANK 2
ECSPI3_MOSI
IO_L1P_CCLK_2
IO_L1N_M0_CMPMISO_2
IO_L2P_CMPCLK_2
IO_L2N_CMPMOSI_2
IO_L3P_D0_DIN_MISO_MISO1_2
IO_L3N_MOSI_CSI_B_MISO0_2
IO_L12P_D1_MISO2_2
IO_L12N_D2_MISO3_2
IO_L13P_M1_2
IO_L13N_D10_2
IO_L14P_D11_2
IO_L14N_D12_2
IO_L16P_2
IO_L16N_VREF_2
IO_L23P_2
IO_L23N_2
IO_L29P_GCLK3_2
IO_L29N_GCLK2_2
IO_L30P_GCLK1_D13_2
IO_L30N_GCLK0_USERCCLK_2
IO_L31P_GCLK31_D14_2
IO_L31N_GCLK30_D15_2
IO_L32P_GCLK29_2
IO_L32N_GCLK28_2
IO_L41P_2
IO_L41N_VREF_2
IO_L43P_2
IO_L43N_2
IO_L45P_2
IO_L45N_2
IO_L46P_2
IO_L46N_2
IO_L48P_D7_2
IO_L48N_RDWR_B_VREF_2
IO_L49P_D3_2
IO_L49N_D4_2
IO_L62P_D5_2
IO_L62N_D6_2
IO_L63P_2
IO_L63N_2
IO_L64P_D8_2
IO_L64N_D9_2
IO_L65P_INIT_B_2
IO_L65N_CSO_B_2
default to slave serial mode
1
C
FPGA_HSWAPEN
EIM_DA14
keep EIM wires as short as possible
BANK 0
B
U800_3
1
D4
C4
B2
A2
D6
C6
B3
A3
B4
A4
C5
A5
B6
A6
C7
A7
D8
C8
B8
A8
D9
C9
B9
A9
D11
C11
C10
A10
G9
F9
B11
A11
B12
A12
B14
A14
F13
E13
C15
A15
D14
C14
B16
A16
IO_L1P_HSWAPEN_0
IO_L1N_VREF_0
IO_L2P_0
IO_L2N_0
IO_L3P_0
IO_L3N_0
IO_L4P_0
IO_L4N_0
IO_L5P_0
IO_L5N_0
IO_L6P_0
IO_L6N_0
IO_L8P_0
IO_L8N_VREF_0
IO_L10P_0
IO_L10N_0
IO_L11P_0
IO_L11N_0
IO_L33P_0
IO_L33N_0
IO_L34P_GCLK19_0
IO_L34N_GCLK18_0
IO_L35P_GCLK17_0
IO_L35N_GCLK16_0
IO_L36P_GCLK15_0
IO_L36N_GCLK14_0
IO_L37P_GCLK13_0
IO_L37N_GCLK12_0
IO_L38P_0
IO_L38N_VREF_0
IO_L39P_0
IO_L39N_0
IO_L41P_0
IO_L41N_0
IO_L62P_0
IO_L62N_VREF_0
IO_L63P_SCP7_0
IO_L63N_SCP6_0
IO_L64P_SCP5_0
IO_L64N_SCP4_0
IO_L65P_SCP3_0
IO_L65N_SCP2_0
IO_L66P_SCP1_0
IO_L66N_SCP0_0
CCLK
+3.3V
AU800
1
2
2
1
2
P3.3V_DELAYED_77
2
2
4.7k, 1% (DNP) 4.7k, 1%
2
1
0.1uF, 6.3V, X5R
R13F
2
1
2
R12F
1
0.1uF, 6.3V, X5R
+GND
1
GND_311
10
0.1uF, 6.3V, X5R
9
2
8
2
7
0.1uF, 6.3V, X5R
6
1
5
1
4
2
3
2
2
10uF, 10V, X5R, 20%
1
Rev:
Id: 15/16
11
H
4
5
6
7
0.1uF, 6.3V, X5R
P3.3V_DELAYED_87
Console/debug UART
FTDI TTL-232R-3V3 cable pinout
Put in a convenient location
1
+3.3V
P3.3V_DELAYED_85
P3.3V_DELAYED_90
A
D10D
CDBM140-G
2
1
K
+3.3V
GND_338
+GND
GPT_CLKIN
2
3
UART3_RXD
UART3_TXD
GPT_CAPIN1 +GND
1
1
D13D
4
5
GND_333
6
+GND
1
3
UART4_RXD
UART4_TXD
UART4_RTS
C10D
GND_334
+GND
4
5
6
1
2
3
4
5
6
GND_339
+GND
2
1
1
A
C19D
P3.3V_DELAYED_89
1
1
2
3
4
5
6
7
Address 0x88
SMB_SCL
SMB_SDA
17
C11D
YXINT
Y+
DOUT/A0
VIO
SCLK
X+
SDAT
GPIO3
VCC
GPIO2
DIN
GND
MODE
GNDPAD
16
15
14
13
12
11
10
9
STMPE811QTR
GND_335
+GND
LCD_XM
LCD_YP
LCD_XP
TS_ANA
MIC_ISO
R20D
1
2
1
2
MIC_CABLE
100k, 1%
Configure GPIO2 as ADC input
To detect play/pause/etc buttons
on headset cable
GND_341
+GND
B
Male 2.54mm 6x1 header
Male 2.54mm 6x1 header
A
GND_336
2
C18D
ESD5Z3.3T1
2
ESD5Z3.3T1
2
A
K
D12D
K
B
1
2
3
4
5
6
1
UART4_CTS
+GND
U11D
2
P12D
1
+3.3V
GND_342
+3.3V
LCD_YM
R19D
10k, 1%
P11D
Male 2.54mm 6x1 header
TS_TOUCHED
1
6
1
100, 1%
2
5
1
1
2
1
2
0.1uF, 6.3V, X5R
2
1
4
R16D
UART2_TXD
Header with RTS/CTS
Useful for modems, BT; shared with battery
Serial + high resolution timer input
Useful for high precision GPS
1
3
2
100, 1%
1
2
3
4
5
6
2
2
1
0.1uF, 6.3V, X5R
1
2
1
2
10k, 1%
2
A
2
2
1
R15D
UART2_RXD
2
D11D
CDBM140-G
K
P10D
R13D
+3.3V
P3.3V_DELAYED_88
2
Note: STMPE811 is mandatory for microphone jack play/pause button detection
A
0.1uF, 6.3V, X5R
Optional resistive touchscreen
Intended for external access
1
Intended for internal module expansion
8
1
3
2
2
2
1
pull-ups on UART inputs to prevent spurious console events
C
C
1
1
2
1
2
R14D
10k, 1%
UART4_RTS
UART3_RXD
2
R12D
10k, 1%
2
1
UART2_TXD
UART2_RXD
Front panel breakout header
R11D
10k, 1%
2
2
1
R10D
10k, 1%
2
2
1
1
+3.3V
1
P3.3V_DELAYED_86
P16D
9
8
7
TS_ANA
6
1
A
10
5
D14D
2
K
11
SPK_L_P
SPK_L_N
SPK_R_P
SPK_R_N
4
3
2
1
1
1
test point (DNP)
J15D
1
SCL
GND
SDA
SA0
GND
INT1
GND
INT2
12
11
10
9
ACCEL_INT
1
4
5
6
7
+3.3V
1
14
2
VDD
C14D
2
SMB_SDA
MMA8452QR1
GND_343
+GND
C15D
GND_332
+GND
1
GND_340
+GND
test point (DNP)
E
Copyright 2014 Andrew "bunnie" Huang
GND_344
+GND
Sheet: /U_16gpio_misc/
File: 16gpio_misc.sch
HRS FH34SRJ-30S-0.5SH(99)
2
VDDIO
BYP
10uF, 10V, X5R, 20%
2
1
1
SMB_SCL
1
test point (DNP)
J14D
1
2
C17D
2
0.1uF, 6.3V, X5R
1
1
2
2
+GND
1
C30U
C16D
GND_331
2
C29U
10uF, 10V, X5R, 20%
bare wire hole
+GND
+5V
+3.3V
2
R18D
330, 1%
+GND
Novena PVT2-A
Title: 16gpio_misc
GND_337
1
LTST-S270KGKT green
+3.3V
12
C64F
GND_345
P5.0V_DELAYED_19
P3.3V_DELAYED_83
P3.3V_DELAYED_84
1
Activity LED / CPU alive
E
P3.3V_DELAYED_91
13
+3.3V
1
D
U10D
2
14
CHG_PWRSWITCH
GPT_CAPIN1
control 5V power on breakout
GPT_CMPOUT3
case open status
KEY_COL3
BT association button
KEY_ROW1
EPIT1_EPITO das blinkenlight
EPIT1_EPITO
short to ground to toggle power
P3.3V_DELAYED_92
1
have fun.
0.1uF, 6.3V, X5R
15
+5V
1
SMT pad
16
1
17
1
test point (DNP)
J13D
1
P5.0V_DELAYED_18
18
1
1
2
19
FPGA_LSPI_MOSI
FPGA_LSPI_HOLD
FPGA_LSPI_CS
Device addr = 0x38
test point (DNP)
J11D
2
20
0.1uF, 25V, X5R
21
1
test point (DNP)
J12D
1
22
1
23
FPGA_LSPI_CLK
FPGA_LSPI_WP
FPGA_LSPI_MISO
2
24
2
25
10uF, 10V, X5R, 20%
D
26
accelerometer
J10D
1
1
27
P5.0V_KBD
USB_KBD_N
USB_KBD_P
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
28
2
29
2
30
0.1uF, 6.3V, X5R
P5.0V_MOUSE
USB_MOUSE_N
USB_MOUSE_P
1
2
3
4
Copyrights:
CC-BY-SA 3.0
5
Patents: Apache
2.0
6
Size: B
Date: 22 12 2014
KiCad E.D.A. eeschema (2014-08-05 BZR 5054)-product
7
Rev:
Id: 16/16
8

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