Euvis 8-GSPS Dual DAC FMC Module, FMC2662 FMC2662 – 8-GSPS 12-bit Dual DAC FMC Module PRODUCT DESCRIPTION The FMC2662 module is equipped with two Euvis MD662H digital-to-analog converters (DAC’s). At 8 GSPS, the module provides analog outputs with bandwidth from DC to 4 GHz (Nyquist bandwidth The 96 LVDS pairs of digital data are fed through two FMC connectors, a high-pin-count (HPC) and a low-pin-count (LPC) connector. The digital data multiplexing ratio is 4:1 and the digital data rate is 2 Gb/s with the DAC’s operating at 8 GSPS. Sampling window select (SEL’s) and reset signals of the two DAC’s can be independently controlled via the FMC connectors. The module includes two clock buffers to relax the need of high-power clock source. Both amplitudes and duty cycles of clock buffers can be programmed though I2C interface or use factory preset values. KEY FEATURES • • • • • Dual 12-bit DAC’s 1 ~ 8 GSPS sampling rate On-board clock buffers with adjustable gain and duty cycle Power supplies needed from carrier: 12V and 3.3 V Compliant with Vita 57.1 standard BLOCK DIAGRAM SMA Connectors FMC Connectors Control 2 2 2 OA_P, OA_N MUX DAC Clock Buffer & Distribution CKI 2 96 2 2 OB_P, OB_N 2 MUX DAC Power Unit Rev (A.3), 3/5/14 2 96 I2C RES ET_A SEL_A DA CK_8 RES ET_B SEL_B DA +12 V +3.3 V 1 Euvis 8-GSPS Dual DAC FMC Module, FMC2662 ELECTRICAL SPECIFICATIONS Symbol Parameter Min Typical Max Unit o Operating Temperature To Sampling Rate fdata 1 8 8 GSPS Clock Frequency fCK 0.5 4 4 GHz PCK +3 +6 +10 dBm Output Frequency fout 0 4 GHz Output Level2 Vout -635 0 mV Pout -4 0 dBm -130 dBC/Hz Clock Input Power 1 Output Power 3 Output Residue Phase Noise Output Port Return Loss Power Supply 25 Nf C RLRF 15 dB V33 +3.3 V I33 300 mA V120 +12 V I120 800 mA 1 Normal operation has usable bandwidth from DC to Nyquist bandwidth, 4 GHz, at 8 GSPS. 2 If external 50-ohm loads are terminated to ground, the analog outputs will have voltage swings from ground to – 0.6 V with a common mode voltage of –0.3 V. If a positive analog output common mode level is desired, the external 50 ohm loads can be terminated to a positive voltage Vpull with a resultant analog output common mode voltage of (Vpull – 0.6)/2. Vpull should not exceed 5 V. 3 10 KHz offset Rev (A.3), 3/5/14 2 Euvis 8-GSPS Dual DAC FMC Module, FMC2662 TERMINAL DESCRIPTION Name Function I/O Signal CKI Input Clock I RF O_AP CH A Analog Output Positive O RF O_AN CH A Analog Output Negative O RF O_BP CH B Analog Output Positive O RF O_BN CH B Analog Output Negative O RF GND Ground DA 48 LVDS Pairs of Digital Data Inputs for CH A I RF DB 48 LVDS Pairs of Digital Data Inputs for CH B I RF RESET_A LVDS Pair inputs for CH A DAC Reset I RF RESET_B LVDS Pair inputs for CH B DAC Reset I RF SEL_A CH A DAC Sampling Window Select I DC SEL_B CH B DAC Sampling Window Select I DC SCK I2C Clock I RF SDA I2C Data I/O RF Rev (A.3), 3/5/14 DC 3 Euvis 8-GSPS Dual DAC FMC Module, FMC2662 SWITCHING CHARACTERISTICS Parameter Description Min Typ Max Units Data, Reset, CK_8: LVDS Logic VIH VIL Input Voltage High Input Voltage Low I Ts Th Input driving current Setup time Hold time 1.4 1 V V 2 mA ns ns 0.2 0.2 SEL: LVCOMS25 / LVCMOS18 Logic VIH Input Voltage High 1.5 2.5 2.8 V VIL I Input Voltage Low Input driving current -0.3 0 250 0.5 V uA I2C SDA, SCK: LVTTL33 Logic Speed Standard Fast VIH High-Speed Input Voltage High VIL I Input Voltage Low Input driving current Cin VHys Input Capacitance Input Hysteresis Rev (A.3), 3/5/14 2 100 400 KHz KHz 3400 3.3 KHz V 0 0.3 1 ±1 V uA 2 pF V 4 Euvis 8-GSPS Dual DAC FMC Module, FMC2662 PIN ASSIGNMENTS Signal Name MDA_RESETP MDA_RESETN MDA_SEL1 MDA_SEL2 MDB_RESETP MDB_RESETN MDB_SEL1 MDB_SEL2 CKD8FP CKD8FN +12V +3.3V Rev (A.3), 3/5/14 FMC Pin Name LPC_LA06P P2.C10 LPC_LA06N P2.C11 LPC_LA01P P2.D8 LPC_LA01N P2.D9 HPC_HA02P P1.K7 HPC_HA02N P1.K8 HPC_HA03P P1.J6 HPC_HA03N P1.J7 HPC_CLK00P P1.H4 HPC_CLK00N P1.H5 12P0V P1.C35 12P0V P1.C37 12P0V P2.C35 12P0V P2.C37 3P3V P1.C39 3P3VAUX P1.D32 3P3V P1.D36 3P3V P1.D38 3P3V P1.D40 3P3V P2.C39 3P3VAUX P2.D32 3P3V P2.D36 3P3V P2.D38 3P3V P2.D40 5 Euvis MUXDAC A Data A11 B11 C11 D11 A10 B10 C10 D10 A9 B9 C9 D9 A8 B8 C8 D8 MUXDAC B Data A11 B11 C11 D11 A10 B10 C10 D10 A9 B9 C9 D9 A8 B8 C8 D8 8-GSPS Dual DAC FMC Module, FMC2662 FMC Pin LPC_LA32P LPC_LA32N LPC_LA33P LPC_LA33N LPC_LA30P LPC_LA30N LPC_LA31P LPC_LA31N LPC_LA28P LPC_LA28N LPC_LA29P LPC_LA29N LPC_LA24P LPC_LA24N LPC_LA25P LPC_LA25N LPC_LA18P LPC_LA18N LPC_LA23P LPC_LA23N LPC_LA21P LPC_LA21N LPC_LA22P LPC_LA22N LPC_LA26P LPC_LA26N LPC_LA27P LPC_LA27N LPC_LA19P LPC_LA19N LPC_LA20P LPC_LA20N P2.H37 P2.H38 P2.G36 P2.G37 P2.H34 P2.H35 P2.G33 P2.G34 P2.H31 P2.H32 P2.G30 P2.G31 P2.H28 P2.H29 P2.G27 P2.G28 P2.C22 P2.C23 P2.D23 P2.D24 P2.H25 P2.H26 P2.G24 P2.G25 P2.D26 P2.D27 P2.C26 P2.C27 P2.H22 P2.H23 P2.G21 P2.G22 MUXDAC A Data FMC Pin HPC_HB17P HPC_HB17N HPC_HB18P HPC_HB18N HPC_HB16P HPC_HB16N HPC_HB19P HPC_HB19N HPC_HB14P HPC_HB14N HPC_HB15P HPC_HB15N HPC_HB12P HPC_HB12N HPC_HB13P HPC_HB13N HPC_HB10P HPC_HB10N HPC_HB11P HPC_HB11N HPC_HB08P HPC_HB08N HPC_HB09P HPC_HB09N HPC_HB06P HPC_HB06N HPC_HB07P HPC_HB07N HPC_HB00P HPC_HB00N HPC_HB01P HPC_HB01N P1.K37 P1.K38 P1.J36 P1.J37 P1.F34 P1.F35 P1.E33 P1.E34 P1.K34 P1.K35 P1.J33 P1.J34 P1.F31 P1.F32 P1.E30 P1.E31 P1.K31 P1.K32 P1.J30 P1.J31 P1.F28 P1.F29 P1.E27 P1.E28 P1.K28 P1.K29 P1.J27 P1.J28 P1.K25 P1.K26 P1.J24 P1.J25 A7 B7 C7 D7 A6 B6 C6 D6 A5 B5 C5 D5 A4 B4 C4 D4 MUXDAC B Data Rev (A.3), 3/5/14 A7 B7 C7 D7 A6 B6 C6 D6 A5 B5 C5 D5 A4 B4 C4 D4 FMC Pin LPC_LA17P LPC_LA17N LPC_LA14P LPC_LA14N LPC_LA13P LPC_LA13N LPC_LA15P LPC_LA15N LPC_LA16P LPC_LA16N LPC_LA11P LPC_LA11N LPC_LA12P LPC_LA12N LPC_LA09P LPC_LA09N LPC_LA10P LPC_LA10N LPC_LA07P LPC_LA07N LPC_LA08P LPC_LA08N LPC_LA05P LPC_LA05N LPC_LA04P LPC_LA04N LPC_LA03P LPC_LA03N LPC_LA02P LPC_LA02N LPC_LA00P LPC_LA00N P2.D20 P2.D21 P2.C18 P2.C19 P2.D17 P2.D18 P2.H19 P2.H20 P2.G18 P2.G19 P2.H16 P2.H17 P2.G15 P2.G16 P2.D14 P2.D15 P2.C14 P2.C15 P2.H13 P2.H14 P2.G12 P2.G13 P2.D11 P2.D12 P2.H10 P2.H11 P2.G9 P2.G10 P2.H7 P2.H8 P2.G6 P2.G7 MUXDAC A Data FMC Pin HPC_LA21P HPC_LA21N HPC_LA22P HPC_LA22N HPC_LA23P HPC_LA23N HPC_LA17P HPC_LA17N HPC_HA23P HPC_HA23N HPC_HA22P HPC_HA22N HPC_HA19P HPC_HA19N HPC_HA20P HPC_HA20N HPC_HA21P HPC_HA21N HPC_HA18P HPC_HA18N HPC_HA17P HPC_HA17N HPC_HA15P HPC_HA15N HPC_HA14P HPC_HA14N HPC_HA11P HPC_HA11N HPC_HA10P HPC_HA10N HPC_HA16P HPC_HA16N P1.H25 P1.H26 P1.G24 P1.G25 P1.D23 P1.D24 P1.D20 P1.D21 P1.K22 P1.K23 P1.J21 P1.J22 P1.F19 P1.F20 P1.E18 P1.E19 P1.K19 P1.K20 P1.J18 P1.J19 P1.K16 P1.K17 P1.F16 P1.F17 P1.J15 P1.J16 P1.J12 P1.J13 P1.K13 P1.K14 P1.E15 P1.E16 A3 B3 C3 D3 A2 B2 C2 D2 A1 B1 C1 D1 A0 B0 C0 D0 MUXDAC B Data A3 B3 C3 D3 A2 B2 C2 D2 A1 B1 C1 D1 A0 B0 C0 D0 FMC Pin HPC_LA06P HPC_LA06N HPC_LA01P HPC_LA01N HPC_LA00P HPC_LA00N HPC_LA05P HPC_LA05N HPC_LA03P HPC_LA03N HPC_LA04P HPC_LA04N HPC_LA08P HPC_LA08N HPC_LA07P HPC_LA07N HPC_HA05P HPC_HA05N HPC_HA04P HPC_HA04N HPC_HA09P HPC_HA09N HPC_HA08P HPC_HA08N HPC_HA07P HPC_HA07N HPC_HA06P HPC_HA06N HPC_HA13P HPC_HA13N HPC_HA12P HPC_HA12N P1.C10 P1.C11 P1.D8 P1.D9 P1.G6 P1.G7 P1.D11 P1.D12 P1.G9 P1.G10 P1.H10 P1.H11 P1.G12 P1.G13 P1.H13 P1.H14 P1.E6 P1.E7 P1.F7 P1.F8 P1.E9 P1.E10 P1.F10 P1.F11 P1.J9 P1.J10 P1.K10 P1.K11 P1.E12 P1.E13 P1.F13 P1.F14 FMC Pin HPC_LA15P HPC_LA15N HPC_LA16P HPC_LA16N HPC_LA14P HPC_LA14N HPC_LA13P HPC_LA13N HPC_LA11P HPC_LA11N HPC_LA12P HPC_LA12N HPC_LA09P HPC_LA09N HPC_LA10P HPC_LA10N HPC_LA25P HPC_LA25N HPC_LA24P HPC_LA24N HPC_LA29P HPC_LA29N HPC_LA28P HPC_LA28N HPC_LA31P HPC_LA31N HPC_LA30P HPC_LA30N HPC_LA33P HPC_LA33N HPC_LA32P HPC_LA32N P1.H19 P1.H20 P1.G18 P1.G19 P1.C18 P1.C19 P1.D17 P1.D18 P1.H16 P1.H17 P1.G15 P1.G16 P1.D14 P1.D15 P1.C14 P1.C15 P1.G27 P1.G28 P1.H28 P1.H29 P1.G30 P1.G31 P1.H31 P1.H32 P1.G33 P1.G34 P1.H34 P1.H35 P1.G36 P1.G37 P1.H37 P1.H38 6 Euvis 8-GSPS Dual DAC FMC Module, FMC2662 BOARD OUTLINE AND DIMENSIONS: TOP VIEW g f e h i OA_P OA_N CKI OB_N MUX MUX DAC DAC A B j d c OB_N b P2 P1 a P1 is the primary HPC connector and P2 is the LPC connector. All dimensions use the bottom left corner of the board as the origin. All dimensions are in millimeters (mm). Board thickness is 1.62 mm. Board Edge Lengths Edge Length Edge Length Edge Length a d g j 139 9.1 131.3 56.9 b e h Width 61.7 2.1 21.9 139 c f i Height 2.4 8 3 78.8 FMC Connector Mount Hole Locations ( x, y ) 73, 18.4 136, 18.4 3, 18.4 66, 18.4 SMA Locations ( x, y ) CKI OA_P OA_N Rev (A.3), 3/5/14 68.3, 68 37.0, 68 47.4, 68 OB_P OB_N 98.8, 68 109.2, 68 7 Euvis 8-GSPS Dual DAC FMC Module, FMC2662 TEST SETUP In applications, FMC2662 requires a VITA 57.1-compliant carrier board to provide all digital data, DAC controls, I2C signal, and DC powers via FMC connectors. The carrier must provide two power supplies, +12V and +3.3V, with minimum current capacities of 1A and 500mA respectively. Digital data and DAC resets are in LVDS pairs. The DAC timing selects and return-to-zero mode select are single-ended LVCMOS25. The carrier board can be an advanced FPGA evaluation board, such as Xilinx VC707, with proper configurations. The FMC module is tested using Euvis carrier FMCC371 as shown in following figure. The carrier consists of a Xilinx XC6VLX130T, a USB controller, and power modules. In the test setup, the carrier is controlled by a PC host via the USB interface. The carrier can store up to 2 x 512 K words of data in memory. The maximum data length is 64 us at 4 GSPS for each channel. Several built-in waveforms are available as in our AWG’s GUI. Waveform generation and download are performed in GUI. Rev (A.3), 3/5/14 8 Euvis 8-GSPS Dual DAC FMC Module, FMC2662 Euvis Inc. Ordering Information: Email to: [email protected] Or call: (805) 583-9888 x108 Sales Department Or fax: (805) 583-9889 The information contained in this document is based on preliminary measured results. Characteristic data and other specifications are subject to change without notice. Customers are advised to confirm information in this advanced datasheet prior to using this information or placing the order. Euvis Inc. does not assume any liability arising from the application or use of any product or circuit described herein, neither does it convey any license under its patents or any other rights. Rev (A.3), 3/5/14 9
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