Sample Exam

CENG 5931
Digital Design and Computer Architecture
Spring 2014
Exam 1
March 3, 2014
You have 80 minutes to complete the exam.
Please write your answers clearly and legibly on this exam paper.
GRADE: ___________
Name: _______________________________. Class ID: _________________.
1. (10 pt) What is the range (minimum and maximum) of values if a 16-bit binary number is given in
unsigned, two’s complement and sign-magnitude formats?
Minimum
Maximum
Unsigned
2’s comp.
Sign-Mag.
2. (5 pt) Convert the following 4-bit numbers to 8-bit numbers
a. assuming they are given in two’s complement format.
01012 
__ __ __ __
__ __ __ __
10102 
__ __ __ __
__ __ __ __
b. assuming they are given as unsigned numbers.
01012 
__ __ __ __
__ __ __ __
10102 
__ __ __ __
__ __ __ __
1
CENG 5931
Digital Design and Computer Architecture
Spring 2014
3. (15 pt) Do the following number conversions assuming two’s complement representation is used for
binary numbers,
a. 12110
= __ __ __ __
__ __ __ __ 2
b. -9910
= __ __ __ __
__ __ __ __ 2
c. 1001 00102
= __________ 10
d. 9FA116
=____ ____ ____ ____2
e. 1100 1010 1100 00112 = __ __ __ __ 16
2
CENG 5931
Digital Design and Computer Architecture
Spring 2014
4. (16 pt) Design a combinational circuit that converts a BCD (Binary Coded Decimal) code to 2-4-2-1
weighted code as shown below. For the six input combinations that do not represent valid BCD
digits, the circuit output should be “XXXX”. Show your work.
Decimal
0
1
2
3
4
5
6
7
8
9
BCD
(X3X2X1X0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
2421 code
(Z3Z2Z1Z0)
0000
0001
0010
0011
0100
1011
1100
1101
1110
1111
Z0 = ______________________________
Z1 = ______________________________
Z2 = ______________________________
Z3 = ______________________________
3
CENG 5931
Digital Design and Computer Architecture
Spring 2014
5. (8 pt) Given the timing values below, what is the minimum clock cycle time (Tc) for the circuit?
CLK
CLK
Timing Characteristics:
t
= 25 ps
ccq
A
t
t
B
C
D
X'
Y'
X
Y
t
t
t
pcq
setup
hold
pd
cd
= 40 ps
= 60 ps
= 70 ps
= 45 ps per gate
= 30 ps per gate
Tc = ____________
4
CENG 5931
Digital Design and Computer Architecture
Spring 2014
6. (16 pt) In this problem, you will design various MUXes.
a. (8 pt) Design a 2-to-1 MUX using logic gates assuming inputs are 1-bit. Show your work
(truth table, K-maps, output equation and block diagram)
b. (8 pt) Design a 4-to-1 MUX using only 2-to-1 MUXes. Show your block diagram.
5
CENG 5931
Digital Design and Computer Architecture
Spring 2014
7. (10 pt) Given the output and next state equations below, draw the block diagram of the
corresponding sequential circuit. Rectangles below represent D flip-flops.
Q2 +
= Q2’· Q0
Q1 +
= X · Q1 + X · Q0’ + Q2 · Q1
Q0 +
= Q2’
Z
= Q1 · Q0’
FF0
FF1
FF2
(2 pt) Is this a Mealy or Moore machine? _______________
6
CENG 5931
Digital Design and Computer Architecture
Spring 2014
8. (10 pt) The block diagram of a sequential circuit is given below.
a. (8 pt) Write down the next state and output equations.
Q1 +
= ______________________________________________
Q2 +
= ______________________________________________
Z
= ______________________________________________
b. (2 pt) Is this a Mealy or Moore machine? ________________
7
CENG 5931
Digital Design and Computer Architecture
Spring 2014
9. (15 pt) Design a sequence detector as Mealy sequential circuit. The circuit has one input (X) and one
output (Z). Z becomes 1 whenever 1010 input sequence occurs. The circuit does NOT reset after a 1
output is generated.
a. (10 pt) Draw a state graph for the sequential circuit.
b. (5 pt) Drive the state table for your state graph in part (a).
8
CENG 5931
Digital Design and Computer Architecture
Spring 2014
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