Freescale – T4240 RDB IRF Proven Power Design with Freescale’s T-Series QorIQ For Complete Design Information http://mypower.irf.com/Freescale 1 Contents & Guidelines of Report • Results show design of scaling processor cores vs. power design from 24 Cores to 4 Cores • IRF and Freescale collaboration of a Power design to scale from T4 to T1 processors – T4240 used to scale the design Core and Memory Power Rails For T4 Designs: IR3565BMFS01TRP For T2/T1 Designs: • Design was verified with Freescale on the RDB/QSS/HSSI designs and given to ODM/IDH partners to seed production level reference designs • This report highlights the advantages of the Digital Power design to “Tune” for actual load parameters and system level processor modes for high performance scaling. Core+DDR: IR36021MFS01TRP Core Only: IR36021MFS02TRP • International Rectifier now offers PRE-CALIBRATED Multi-phase Power devices optimized for Freescale T-Series QorIQ Processors to meet the dynamic, tight design requirements from 10A to 80A for the core and memory rails. • All other IR devices in the power solution are standard (SupIRBucks & FETs) for the peripheral & I/O rails. IRF Power on the following: T4240, T2080, T1042, T1040, more coming… 2 T4240 – VCORE & DDR Sol’n Overview IR3565B , 4+2-Phase Dual Output Digital Controller IR3550, 60A PowIRstage FP1007R3-R15-R Inductor on 4-Phase VCORE (Fsw = 500kHz) L = 150nH / DCR = 0.29mOhm & Csen = 220nF Set Rsen = 2.40kOhm (Rsen >= L/DCR/Csen) Rcs = 3.40kOhm, Rs1_s2 = 2.87kOhm, Ccs = 100pF Rll ~ 1.0mOhm & AVP BW ~ 192kHz IHLP-4040-DZ Powdered Iron Inductor on 2-Phase DDR (Fsw = 500kHz) L = 360nH / DCR = 1.30mOhm & Csen = 220nF Set Rsen = 1.30kOhm (Rsen >= L/DCR/Csen) Rcs = 2.43kOhm, Rs1_s2 = 1.80kOhm, Ccs = 120pF Rll ~ 2.5mOhm & AVP BW ~ 200kHz 3 T4240 – VCORE (Loop 1) – NTC & LL Comp 4 T4240 – DDR (Loop 2) – NTC & LL Comp 5 iScale, iGain, and Offsets – DC Calibration Loop_1_iscale = 581 dec = 0x0245 ~ 92.87% of nominal Rll scaling Loop_1_i_gain = 1 dec = 0x01 ~ 4x AFE Gain 1.0mOhm * 0.9287 = 0.9287mOhm Actual Rll from RCSP/RCSM Circuit (DCR is acting ~ 7.7% high… 0.29mOHm * 1.077 ~ 0.312mOhm effective DCR) Offsets 0.0A Offset Req’d (0.5A LSB optional +3.5A/-4.0A) 0.0mV Offset Req’d (5mV LSB optional +40mV/-35mV) Loop_2_iscale = 215 dec = 0x00D7 ~ 85.92% of nominal Rll scaling Loop_2_i_gain = 0 dec = 0x00 ~ 2x AFE Gain 2.5mOhm * 0.8592 = 2.148 mOhm Actual Rll from RCSP/RCSM Circuit (DCR is acting ~ 16.4% high… 1.30mOHm * 1.164 ~ 1.513mOhm effective DCR) Offsets 0.0A Offset Req’d (0.5A LSB optional +3.5A/-4.0A) 0.0mV Offset Req’d (5mV LSB optional +40mV/-35mV) 6 T4240 – VCORE – Load Model 7 T4240 – VCORE – PID Tuning & Bode Model 8 T4240 – VCORE – Actual BODE – Stable PIDs 9 T4240 – VCORE – Actual BODE – Unstable PIDs 10 T4240 – Vcore – PID Tuning & BODE Analysis VCORE STABLE SETTINGS (Bode Optimized – used these!) Kp = 34, Ki = 30, Kd = 48, LPF1 = 4, LPF2 = 9 Modeled Data PM = 35.1deg GM = 22.5dB BW = 36.5kHz Real Data 77.6deg 20.8dB 71.6kHz VCORE UNSTABLE SETTINGS (Response Optimized) Although the Vout response looked marginally better, overall stability and robustness / loop-stability is a concern. Loop stability calls for Loop BW << 1/5 Fsw. Fsw = 500kHz. So, our Loop BW should be << 100kHz. Kp = 36, Ki = 32, Kd = 53, LPF1 = 4, LPF2 = 9 Modeled Data Real Data PM = 62.1deg 78.8deg GM = 15.5dB 10.3dB BW = 50.0kHz 149.6kHz 11 ORIGINAL PIDs – 16A Loadstep (37.5A – 53.5A) 24 COREs using Freescale Dhrystone Code Vmin = 1.026V Vmax = 1.084V Droop ~ 24.0mV Overshoot ~ 34.0mV TOB = +/- 30.0mV TOB = +/- 30.0mV Margin = 6.0mV Margin = (-)4.0mV 12 STABLE PIDs – 16A Loadstep (37.5A – 53.5A) 24 COREs using Freescale Dhrystone Code Vmin = 1.0250V Vmin = 1.0255V Droop ~ 25.0mV Droop ~ 24.5mV TOB = +/- 30.0mV TOB = +/- 30.0mV Margin = 5.0mV Margin = 5.5mV 13 UNSTABLE PIDs – 16A Loadstep (37.5A – 53.5A) 24 COREs using Freescale Dhrystone Code Vmin = 1.0300V Vmin = 1.0322V Droop ~ 20.0mV Droop ~ 17.8mV TOB = +/- 30.0mV TOB = +/- 30.0mV Margin = 10.0mV Margin = 12.2mV 14 STABLE PIDs – 16A Load-Release (53.5A – 37.5A) 24 COREs using Freescale Dhrystone Code Vmax = 1.0796V Vmax = 1.080V Overshoot ~ 29.6mV Overshoot ~ 30.0mV TOB = +/- 30.0mV TOB = +/- 30.0mV Margin = 0.4mV Margin = 0.0mV 15 UNSTABLE PIDs – 16A Load-Release (53.5A – 37.5A) 24 COREs using Freescale Dhrystone Code Vmax = 1.0760V Vmax = 1.0788V Overshoot ~ 26.0mV Overshoot ~ 28.8mV TOB = +/- 30.0mV TOB = +/- 30.0mV Margin = 4.0mV Margin = 1.2mV 16 STABLE PIDs – 5A Loadstep (37.5A – 42.5A) 8 COREs using Freescale Dhrystone Code Vmin = 1.0409V Vmin = 1.0402V Droop ~ 9.1mV Droop ~ 9.8mV TOB = +/- 30.0mV TOB = +/- 30.0mV Margin = 20.9mV Margin = 20.2mV 17 STABLE PIDs – 5A Load Release (42.5A – 37.5A) 8 COREs using Freescale Dhrystone Code Vmax = 1.0638V Vmax = 1.0629V Overshoot ~ 13.8mV Overshoot ~ 12.9mV TOB = +/- 30.0mV TOB = +/- 30.0mV Margin = 16.2mV Margin = 17.1mV 18 T4240 – DDR Load Model 19 T4240 – DDR PID Tuning & Bode Model 20 T4240 – DDR Actual BODE Stable (used!) 21 T4240 – DDR – PID Tuning & BODE Analysis DDR STABLE SETTINGS (Bode Optimized – used these!) Kp = 35, Ki = 32, Kd = 52, LPF1 = 4, LPF2 = 9 Modeled Data PM = 56.1deg Real Data 61.7deg GM = 17.3dB BW = 41.0kHz 24.1dB 32.4kHz 22
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