Role of mask on the contact
etching for 14nm nodes
MEBARKI Mokrane1,2,3
Maxime Darnon2, Cecile Jenny1, Nicolas Posseme3, Delia Ristoiu1, Germain Servanton1, Olivier Joubert2
1
ST Microelectronics
Laboratoire des technologies de la microélectronique (LTM) CNRS
3 CEA LETI
2
PESM
Monday, May 12 2014
Grenoble, France
Outline
Double patterning for contact etching
• Double patterning strategy
Mask Opening
• Comparison between N2/H2 vs COS/O2
Silicon oxide etching
• Interaction with OPL mask opening process
Conclusion
PESM 2014- [email protected]
2
Double patterning for contact etching:
3
Increase the number of
transistors on a chip
Reduce the transistors
dimension
Change of contacts
patterning strategy
Double patterning
First patterning
Si3N4
1. TiN deposition
PESM 2014- [email protected]
Double patterning for contact etching:
3
Increase the number of
transistors on a chip
Reduce the transistors
dimension
Change of contacts
patterning strategy
Double patterning
First patterning
Si3N4
1. TiN deposition
2. Trilayer line
pattern
Cross section post
OPL etching
PESM 2014- [email protected]
Double patterning for contact etching:
3
Increase the number of
transistors on a chip
Reduce the transistors
dimension
Change of contacts
patterning strategy
Double patterning
First patterning
TiN Hard mask
Si3N4
1. TiN deposition
2. Trilayer line
pattern
3. Post etching of
section
post
TiNCross
hard
mask
OPL etching
PESM 2014- [email protected]
Double patterning for contact etching:
4
Increase the number of
transistors on a chip
Reduce the transistors
dimension
Change of contacts
patterning strategy
Double patterning
Second patterning
(Cross section)
TiN Hard mask
Si3N4
1. Post etching of
TiN hard mask
TiN Hard mask
2. Trilayer OPL
mask
Crosspattern
section post
OPL etching
PESM 2014- [email protected]
Double patterning for contact etching:
4
Increase the number of
transistors on a chip
Reduce the transistors
dimension
Change of contacts
patterning strategy
Double patterning
Second patterning
(Cross section)
TiN Hard mask
TiN Hard mask
Si3N4
1. Post etching of
TiN hard mask
2. Trilayer OPL
mask pattern
3. Post OPL
mask etching
PESM 2014- [email protected]
Double patterning for contact etching:
4
Increase the number of
transistors on a chip
Reduce the transistors
dimension
Change of contacts
patterning strategy
Double patterning
Second patterning
(Cross section)
TiN Hard mask
Contact TiN Hard mask
Si3N4
1. Post etching of
TiN hard mask
2. Trilayer OPL
mask pattern
3. Post OPL mask
etching
4. Post Silicon
oxide etching
PESM 2014- [email protected]
Double patterning for contact etching:
5
OPL strip
Post contact etching
Double patterning
TEOS
opening
TiN
TiN
TiN
TEOS
Contact
opening
SEM Top view post contact etching
SEM cross section post contact etching
PESM 2014- [email protected]
Double patterning for contact etching:
6
Increase the number of
transistors on a chip
Reduce the transistors
dimension
Change of contacts
patterning strategy
Double patterning
Second patterning
(Cross section)
TiN Hard mask
TiN Hard mask
Si3N4
1. Post etching of
TiN hard mask
TiN Hard mask
2. Trilayer OPL
mask pattern
3. Post OPL
mask etching
Contact
4. Post Silicon oxide
etching
PESM 2014- [email protected]
Characteristics of OPL etching:
7
OPL etching With N2/H2
OPL etching With COS/O2(5%)
SiARC
Etch rate of OPL according the COS ratio
SiARC
OPL
TiN
OPL
TiN
TEOS
TEOS
Consumption of SiARC
Presence of undercut on
sidewalls of OPL mask
OPL etching With COS/O2(17%)
and shorter over etch
The increase of COS ratio leads a
better conservation of OPL mask.
SiARC
TiN
OPL
TEOS
TEOS
PESM 2014- [email protected]
Characteristics of OPL etching:
8
EDX analysis after OPL etching with COS/O2(5%) chemistry :
SiARC
SiARC
observation :
Si3N4
Ti
OPL
OPL
TiN
TEOS
EDX analysis for Ti element
Presence of Ti elements
TiN
TEOS
S
EDX analysis for S element
EDX analysis after OPL etching with N2/H2 chemistry :
SiARC
OPL
No significant TiN sputtering
OPL
TiN
TiN
TEOS
TEOS
TEM cross section
EDX analysis
TEOS
Interaction between
OPL etching and TiN hard mask
PESM 2014- [email protected]
Double patterning for contact etching:
9
Increase the number of
transistors on a chip
Reduce the transistors
dimension
Change of contacts
patterning strategy
Double patterning
Second patterning
(Cross section)
TiN Hard mask
Contact TiN Hard mask
Si3N4
1. Post etching of
TiN hard mask
2. Trilayer OPL
mask pattern
3. Post OPL mask
etching
4. Post Silicon
oxide etching
PESM 2014- [email protected]
Interaction with mask opening process:
10
Etch-stop presence after contact etching
for the OPL opening with COS/O2(5%)
OPL etching with COS/O2 :
Post contact etching
TiN
TEOS
Taper profiles
TEOS
TiN
The contacts are open after contact
etching for the OPL opening with N2/H2
OPL etching with N2/H2 :
Post contact etching
TiN
TEOS
Correct profiles
PESM 2014- [email protected]
Interaction with mask opening process:
11
EDX analysis after oxyde etching :
TiOF
OPL
TiN
OPL
TiN
TEOS
Contact
TEOS
Contact
EDX after oxide etching with COS/O2 (5%) for OPL Opening
Veil formation of TiOxFy on the holes patterned
PESM 2014- [email protected]
Origin of veil formation:
12
OPL etching with COS/O2(5%)
OPL etching with N2/H2
SiARC
SiARC
Ti
OPL
OPL
TiN sputtering
Ti residue
TiN
TiN
No significant TiN
sputtering
TEOS
TEOS
EDX analysis
EDX analysis
Hypothesis : Ti sputtering during
OPL Over Etch induces veil
formation
during
After contact etching for OPL
etching
withSiO
COS/O
2 etching
2(5%)
Decrease OE time
Lower OE
Lower TiN sputtering
No TiOF veil
PESM 2014- [email protected]
Conclusion:
OPL etch
N2/H2
COS/O2
Taper OPL mask profile
Straight OPL mask profile
Low TiN sputter
TiN sputter
Increase ratio of COS/O2
Oxyde etch
Veil formation
Correct Etching
Etch stop
At long OE
Contacts open
At short OE
PESM 2014- [email protected]
PESM
Monday , May 12 2014
Grenoble, France
Thank you for your attention !
PESM 2014- [email protected]