Delivering IP the Way Chip Designers Want Martin Lund EDPS Monterey, CA April 18, 2014 Big trends are driving market growth Mobility 250M+ tablets in 2014 Internet of Things 50B devices by 2020 Cloud Computing 3.3 ZB traffic with 25% CAGR Sources: idc.com cisco.com marketsandmarkets.com Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence. ©2014 Cadence Design Systems, Inc. All rights reserved. Great opportunities for creative technology Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence. ©2014 Cadence Design Systems, Inc. All rights reserved. Challenges Incredible pace of innovation 1st June 2007 Black Jack Jan 2007 Shine Feb 2007 3G Instinct Symbian June 2008 Feb 2008 July 2008 Omnia Chocolate Dec 2008 Oct 2008 3GS June 2009 Galaxy Jun 2009 GGW 550 4 Galaxy Lite Jun 2009 June 2010 Nov 2009 Galaxy S Cosmos Mar 2010 4S Jun 2010 Galaxy S II Optimus Black Oct. 2011 May 2011 Jan 2011 Galazy Note 5 Sep 2011 Viper 4G Samsung photos courtesy of http://www.pcmag.com/slideshow/story/309047/samsung-s-smartphone-history-from-zero-to-galaxy-s4/10 Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence. ©2014 Cadence Design Systems, Inc. All rights reserved. Galazy S III Apr 2012 Sept. 2012 5S 5C May 2012 Optimus Galazy S4 Oct 2012 Sept 2013 Mar 2013 G Flex Oct 2013 Increasing time-to-market pressures 1st June 2007 Black Jack Jan 2007 Shine Feb 2007 3G July 2008 Instinct June 2008 Omnia Dec 2008 Symbian Feb 2008 Chocolate Oct 2008 3GS June 2009 Galaxy Jun 2009 GGW 550 4 Galaxy Lite Jun 2009 June 2010 Nov 2009 Galaxy S Cosmos Mar 2010 4S Jun 2010 Galaxy S II Optimus Black Oct. 2011 May 2011 Jan 2011 Galazy Note 5 Sep 2011 Viper 4G Samsung photos courtesy of http://www.pcmag.com/slideshow/story/309047/samsung-s-smartphone-history-from-zero-to-galaxy-s4/10 Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence. ©2014 Cadence Design Systems, Inc. All rights reserved. Galazy S III Apr 2012 Sept. 2012 5S 5C May 2012 Optimus Galazy S4 Oct 2012 Sept 2013 Mar 2013 G Flex Oct 2013 Big changes with each new generation Kindle 2007 Kindle Touch 2011 Kindle Fire HD 2012 Kindle Fire HDX 2013 Processor 1 x ARM 11* 1 x ARM A8 2 x ARM A9 4x ARM A15** Storage 250MB 4GB Up to 64GB Up to 64GB Display 4 grayscale levels 16 grayscale levels 1920x1200 HD 2560x1600 HD Interfaces Keyboard, CDMA Touch screen, 3G, Wi-Fi Touch screen, 4G LTE, dual-band Wi-Fi, Bluetooth, HDMI, accelerometer, gyro, Dolby audio, HD front camera Touch screen, 4G LTE, dual-band Wi-Fi, Bluetooth, HDMI, accelerometer, gyro, Dolby audio, HD front camera, 8MP rear camera Notes: * Kindle’s Marvell Xscale CPU core comparable to ARM 11 ** Kindle Fire HDX’s Qualcomm Snapdragon CPU cores comparable to ARM A15 Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence. ©2014 Cadence Design Systems, Inc. All rights reserved. Ever changing standards DDR1 DDR4 ©2014 Cadence Design Systems, Inc. All rights reserved. AMBA® 3 AXI™ AMBA® 4 ACE™ PCI Express PCI Express Gen1 Gen3 New packaging technologies 2.5D and 3D packaging Much more complexity Thermal constraints Reliability Cost Through Silicon Vias Stacked die Package-on-package ©2014 Cadence Design Systems, Inc. All rights reserved. New semiconductor technologies ©2014 Cadence Design Systems, Inc. All rights reserved. Creative Solutions Required Systems oriented design approach IP DSP Systems Verification Implementation Features Silicon Power Package Software Cost Memory Interfaces Protocols Standards Constraints ©2014 Cadence Design Systems, Inc. All rights reserved. IP Typical SoC design DDR, LPDDR WideIO HBM, HMC SD, SDIO eMMC NAND ONFi Toggle ADC DAC Ethernet CPU / GPU DSP PCIe SoC PVT Baseband USB Audio / Voice Custom logic Memory Image / Video PLL DLL SSIC M-PCIe ©2014 Cadence Design Systems, Inc. All rights reserved. MIPI LDO POR HDMI DP Systems peripherals If all you have is a hammer – everything looks like a nail ©2014 Cadence Design Systems, Inc. All rights reserved. Dedicated logic is the most efficient answer, right? • Conventional wisdom: dedicated logic up to 1000x more efficient than CPUs • True only in special circumstances: minimal memory references per op • For memory-intensive tasks, fixed logic little better than best processor methods ©2014 Cadence Design Systems, Inc. All rights reserved. M Horowitz, ISSCC 2014, from D. Markovic, 2013 Data processing and the three sweet-spots Application characteristics: Software diversity Computation intensity (ops/sec) Memory Bandwidth (B/op) ©2014 Cadence Design Systems, Inc. All rights reserved. CPU Data processors (DSP, DPU, GPU) Hardwired RTL Integrating multiple functions onto one core Flexibility and efficiency AEC Wideband AMR Wideband DAB/MP2 DRM Dolby Digital Dolby DM3Plus Dolby MS10 Dolby Prologic Dolby TrueHD DRA DTS Boost DTS HD DTS Symmetry FLAC MP3 MPEG-4 aacPlus mSBC Ogg Vorbis SBC Bluetooth WMA WMA 10 Pro AMR Speech G722 Speech G.729AB Speech SILK Speech GSM-FR Speech G726 Speech Tensilica HiFi DSP ©2014 Cadence Design Systems, Inc. All rights reserved. Systems Verification 80% of SoC development costs come from software, verification, and validation OS Middleware Firmware Drivers Software Verification and Validation Physical Implementation IP Qualification 65nm (354M) 40nm (615M) 28nm (1044M) 20nm (1317M) 16/14nm (1636M) Source: IBS July 2013 Process Node (# transistors) ©2014 Cadence Design Systems, Inc. All rights reserved. . Need scalable solution for metric-driven verification Traditional approach Scalable approach Plan Robust SQL database Spreadsheets Scripts Lists Synchronous data Real-time reports Measure/ Analyze Construct Execute Incisive® vManager verification planning and management solution ©2014 Cadence Design Systems, Inc. All rights reserved. 2X Productivity Hardware acceleration is essential for today’s SoCs Palladium® XP II Verification Computing Platform ©2014 Cadence Design Systems, Inc. All rights reserved. Concurrent software development with hybrid verification technology Start SW validation up to six months earlier Virtual Prototyping ARM® Fast Models Acceleration & Emulation SpeedBridge Adapters 60 X faster OS boot Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence. ©2014 Cadence Design Systems, Inc. All rights reserved. FPGA Prototyping Implementation Late bugs kill time-to-market Quarters Months Weeks Days Specification IP and design Verification and integration Physical implementation Fabrication ©2014 Cadence Design Systems, Inc. All rights reserved. IP implementation is increasingly complex PAST TODAY Megahertz signals Simple static timing analysis Static power analysis Gigahertz signals Package and board effects Signal integrity analysis Analog channel models Dynamic power analysis Advanced library characterization ©2014 Cadence Design Systems, Inc. All rights reserved. Requirements for IP today ©2014 Cadence Design Systems, Inc. All rights reserved. IP requires comprehensive EDA support System design HW/SW co-design DDR, LPDDR WideIO HBM, HMC SD, SDIO eMMC NAND ONFi Toggle Ethernet CPU / GPU DSP Logic designPCIe Baseband USB Custom logic Audio / Voice Memory Image / Video Digital SSIC implementation M-PCIe MIPI LDO POR PLL DLL HDMI DP Systems peripherals Signoff and manufacturing Verification ©2014 Cadence Design Systems, Inc. All rights reserved. Custom, analog, ADC mixed-signal DAC design and implementation PVT PCB and IC package design Today’s SoCs require closer collaboration than ever before – from IP through manufacturing IP OEM INNOVATION Tools Foundry Software ©2014 Cadence Design Systems, Inc. All rights reserved. © 2013 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, CDNLive, and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
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