Tutorial 9

Experiment No. 9
Interrupts and Interrupt Handling Routines
The Intel 8259 is a family of Programmable Interrupt Controllers (PICs) designed and developed for
use with the Intel 8085 and Intel 8086 8-bit and 16-bit microprocessors. The family originally
consisted of the 8259, 8259A, and 8259B PICs, though a number of manufactures make a wide range of
compatible chips today. The 8259 acts as a multiplexer, combining multiple interrupt input sources into a
single interrupt output to interrupt a single device.
Figure 1shows the main connectors on an 8259 which are as follows: eight interrupt input request lines
named IRQ0 through IRQ7, an interrupt output line named INT, interrupt acknowledgement line named
INTA, D0 through D7 for communicating the interrupt level or vector offset. Other connectors include
CAS0 through CAS2 for cascading between 8259s. Up to eight slave 8259s may be cascaded to a master
8259 to provide up to 64 IRQs. 8259s are cascaded by connecting the INT line of one slave 8259 to the
IRQ line of one master 8259.
Figure 1: The pin-out diagram of the 8259 PIC.
Almost all microcomputer systems use interrupts to reduce software overhead when controlling
peripherals. However, the number of interrupt pins on a CPU is limited. When the number of interrupt
lines increases beyond that limit, external circuit like 8259 become necessary. There are one interrupt
connected directly to the CPU; Non-Maskable Interrupt (NMI) with vector number 2. Figure 2 shows
how the NMI and the 8259 are connected to the CPU in the MTS-96C kit.
Figure 2: the NMI and the 8259 PIC circuit connection.
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The 8259 can process eight interrupt requests according to an allocated priority order and transmit
the signal with the highest priority to the CPU. It also supplies the CPU with information to ascertain the
interrupt routine start address.
When an interrupt occurred the CPU will execute the interrupt handler. An interrupt handler, also
known as an Interrupt Service Routine (ISR), is a subroutine whose execution is triggered by the
reception of an interrupt.. These handlers are initiated by either hardware interrupts or interrupt
instructions in software, and are used for servicing hardware devices and transitions between protected
modes of operation such as system calls.

Programming 8259 interrupt controller
There are two types of 8259 control words; Initialization Control Words (ICWs) and Operation
Control Words (OCWs). Normally pin A0 is used to select the different control type. When A0 is equal
to 0, register ICW1, OCW2, OCW3 can be accessed. When A0 is equal to 1, register ICW2, ICW3,
ICW4, OCW1 can be accessed.
 The base address for 8253 is 0FFD8h
address
A1
0FFC8H
0
0FFCAH 1
Address allocated to
ICW1, OCW2, and OCW3 Registers
ICW2, ICW3, ICW4, and OCW1 Register
 Initialization Control Words (ICWs)
There are four Initialization Control Words (ICW1 - ICW4).
Notes: set IC4 since the kit has 8086 processor. Set SNGL since we will deal with it in single mode. Choose Level
or Edge trigger, but edge is recommended. Bits D7 D6 D5 D2 are don’t care for 8086 processors
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Note: ICW2 contains the base address of Interrupt vector number. IR0 has the vector no. equals the base vector no.
and IR1 equals the base+1, and so on.
is configured in the cascade mode. We don’t have to configure it in the single mode operation.
Notes: ICW4 is programmed for 8086/8088 processors, and not for 8085. D4 D3 D2 are don’t cares in the single
mode operations. Set D0 for 8086 processor in the kit. Auto EOI resets the interrupt request bit in the interrupt
status register and does not modify priority. Auto EOI is recommended since it will reduce the ISR time. If
Normal EOI is chosen, OCW2 command must be configured in the ISR. In the OCW2 you have to select one of
eight ways that the 8259 will respond to interrupt:
1- Nonspecific End-of-Interrupt: Command sent by the ISR to signal the end of the interrupt. 8259 determines which
interrupt level was active and re-enable the correct interrupt status register bit this will allow the interrupt to take
action again or a lower priority interrupt to take effect.
2- Specific End-of-Interrupt: A command that allows a specific interrupt request to be reset. The highest priority
interrupt input is chosen using the L2–L0 bits (IR0-IR7) of OCW2.
3- Rotate-on-Nonspecific EOI: functions exactly like the Nonspecific End-of-Interrupt command, except it rotates
interrupt priorities after resetting the interrupt status register bit. The level reset by this command becomes the
lowest priority interrupt, i.e. if IR4 was just serviced by this command, it becomes the lowest priority interrupt
input and IR5 becomes the highest priority.
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4- Rotate-on-Automatic EOI: This is used in the applications where all the interrupting devices are of equal priority.
This command must be sent once to the 8259 (set). If this mode must be turned off, (clear) command is used.
5- Rotate-on-Specific EOI: Functions as the specific EOI, except that it selects rotating priority.
6- Set priority: Allows the programmer to set the lowest priority interrupt input using the L2–L0 bits (IR0-IR7) of
OCW2.
 Operation Control Words (OCWs)
There are three Operation Control Words (OCW1 – OCW3).
Note: when a bit is set, it will turn off (mask) the corresponding interrupt input. OCW1 is written since
the mask bits are unknown when the 8259 is firstly initialized. To set IR0, OCW1will be FEH.

Configure the Interrupt Vector Table (IVT):
IVT has a reserved area from 0000H to 0080H physical address (00H-20H vector types). This
area contains the pointers for known service routines such as divide error interrupt and overflow
interrupt. NMI ISR pointer is saved in this reserved area. NMI has a vector type (number) 2, which
means that the addresses 0008H-000BH contain the pointer of the ISR for NMI interrupt; i.e. 0008H and
0009H have the offset value and 000AH-000BH has the segment value of the ISR that will be executed
when the NMI occurred.
After 0080H physical address in the IVT the user can save pointers for his routines that will be
executed when once 8259 interrupts occurred. In this experiment we will choose 20H as a base vector
type for the 8259 module in the kit; i.e. 80H (20Hx4)-81H will have the offset and 82H-83H will have
the segment of the ISR that you will write in your code in this experiment (IR0).
In order to save the address of you ISR in the IVT, you have to find the values of the segment:
offset of your ISR. In your code, the segment is undoubtedly CS, the offset can be found by (OFFSET
ISR_lable). Now you have the needed information, move them to the IVT for each interrupt (see the code
in the box).
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; Constants.
Vec
CODE
EQU _______ ; Vec equals the vector number (type) of the interrupt
SEGMENT
ASSUME
CS: CODE, DS: CODE
START:
CLI
; Clear interrupt
MOV SP, 2000H
MOV AX, CS
MOV DS,AX
MOV
MOV
MOV
MOV
MOV
AX, 0
ES, AX
BX, Vec*4
ES:WORD PTR[BX], OFFSET ISR_NAME
ES:WORD PTR[BX+2],CS
;For each interrupt( IR0-IR7 and NMI)
ICW1:
; Configure ICW1, using OUT instruction(for each IR0-IR7) only
ICW2:
; Configure ICW2, using OUT instruction(for each IR0-IR7) only
ICW4:
; Configure ICW4, using OUT instruction(for each IR0-IR7) only
OCW1:
; Configure OCW1, using OUT instruction(for each IR0-IR7) only
STI
; Set interrupt
JMP $
; Waiting for an interrupt
ISR_NAME:
; Interrupt Service Routine ; for each interrupt( IR0-IR7 and NMI)
OCW2:
; Configure OCW2, using OUT instruction ( if Normal EOI is selected)
IRET
CODE
; Return to main routine
ENDS
END START
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