Outline SoC interconnect diagram

Section 3. Exception Processing
NVIC and Its Functions
Outline
• 
• 
• 
• 
Basic Exception Concepts
Nested Vector Interrupt Controller
Registers and Vector table
Example module
–  Timer Module
1
Basic Concepts of Interrupt Processing
•  A variety of unexpected events in a computer system
–  I/O events, error conditions, network events etc
•  These events are handled by interrupt processing
–  Speed disparity of various devices in a computer
–  Allow multiple and parallel processing of tasks
•  An analogous example: A reading process
– 
– 
– 
– 
– 
Phone rings--à Recognition of an event
Answer the phone or not? à Priority
Book mark the page à store context
Answer the phone à handler
Continue the reading process after phone conversation à done
3
NVIC (Nested Vector Interrupt Controller)
•  Low latency Interrupt
–  12 cycles to PUSH on ISR entry
–  12 cycles to POP on ISR exit
•  Up to 120 interrupt sources
–  Includes 16 ARM core specific exceptions
–  The remaining are modules specific
2
Necessary Procedure of an Interrupt Process
•  Interrupt requester ßà CPU
•  Recognition of an interrupt request:
–  Interrupt requester makes an interrupt request
–  CPU recognizes the interrupt request
•  Prioritization: Determining whether granting the request or not
–  Requester provides its priority
–  CPU compares it with the priority of its current process
•  Context saving to be able to come back after interrupt
–  Program counter marks where interrupt happened
–  Status register and possible other necessary context information
4
SoC interconnect diagram
•  Any module capable of generating an interrupt will depend
on NVIC operation
•  NMI can be generated from:
–  External pin (must configure the MUX)
–  CoreSight Embedded Trace Buffer (ETB)
•  Arm supports 0-255 priority levels, K-70 support 16
priority levels, all fully programmable (0 highest)
–  Reset, NMI and Hard Fault have predefined priority
•  Change Interrupt Priority dynamically
•  Relocable vector table
5
6
Exceptions and Interrupts
NVIC
7
8
Wake-up Sources
Sequence of register setups
The steps for enabling an interrupt on NVIC:
–  1. Enable the peripheral to be used
–  2. Set the proper bit on the NVICSERx to enable the interrupt on
the NVIC
–  3. Clear any pending interrupt by writing to the NVICCPRx to
avoid any spurious interrupt
–  4. Configure the interrupt priority by writing to the NVICIPxx
–  5. Write the ISR
–  6. Enable global interrupts
9
10
!"#$%&'()*+%#,-.%#/01*
!"#"$
%&'())*+',-.'/0(,1/',2(3/4'()4
!"#$%&'()'*+,-.%&'()'*+,/$0#1234#03$2562784#$9"27"$254#00:;43$80#$8742<#=$>##$4"#$0#1234#0$
3:??80@$25$!8AB# C.D$E5$;81# C.F$GE0$4"#$0#1234#0$84402A:4#3=
!"#$A24$833215?#543$80#H$
31
0
ACTIVE bits
Chapter 3 Chip Configuration
Example Registers: NVIC_ISER0-7
Example Registers
ARM Cortex-M4
core
9:;<( !=>,%-12,;/',:44/3&?(&'4
Interrupts
1/'4
Nested Vectored
Interrupt Controller
OFPH-Q
(NVIC)
PPB
Module
@:?(
A*&.'/7&
*(!'&M
'54#00:;4$8742<#$GB813H
-$R$254#00:;4$5E4$8742<#
Module
P$R$254#00:;4$8742<#=
Module
Interrupt Priority Registers
Figure 3-2. NVIC configuration
Table 3-2. Reference links to related
informationprovide an 8-bit
•  The NVIC_IPR0-NVIC_IPR59
registers
priority field for each interrupt and each register holds four
priority fields. These registers are byte-accessible.
*$A24$0#863$83$E5#$2G$4"#$3484:3$EG$4"#$7E00#3;E56251$254#00:;4$23$8742<#$E0$8742<#$856$;#56251=
!"#"5
Topic!"#$%&'()'I,-.%&'()'I,JK$0#1234#03$;0E<26#$85$L.A24$;02E024@$G2#B6$GE0$#87"$254#00:;4$856$
Related module
Reference
#87"$0#1234#0$"EB63$GE:0$;02E024@$G2#B63=$!"#3#$0#1234#03$80#$A@4#.877#332AB#=$>##$4"#$0#1234#0$
Full description
Nested Vectored
http://www.arm.com
3:??80@$25$!8AB#
C.D$E5$;81#
C.F$GE0$4"#20$84402A:4#3=$M87"$0#1234#0$"EB63$GE:0$;02E024@$G2#B63$83$
Interrupt
Controller
3"E95H
(NVIC)
System memory 31
map
Clocking
IPR59
System
memory map
8 7
16 15
PRI_238
...
ARM Cortex-M4 core
PRI_4n+3
PRI_4n+2
ARM Cortex-M4 core
PRI_4n+1
PRI_4n
PRI_1
PRI_0
...
IPRn
0
Clock distribution
PRI_236
PRI_237
Power management
...
Private Peripheral Bus
(PPB)
PRI_3
PRI_2
3.2.2.1 IPR0Interrupt
priority levels
This device supports 16 priority levels for interrupts. Therefore,
in the NVIC each source
9:;<( !=B,%62,;/',:44/3&?(&'4
K70
supports
16 priority
for interrupts.
Therefore,
in the
IPR
registers contains
4 bits. levels
For example,
IPR0 is shown
below: in the NVIC each
1/'4,
@:?(
A*&.'/7&
source in the IPR registers contains 4 bits. For example, IPR0 is shown below:
OFPHDCQ$
31
ODFHPTQ$
R
I02E024@N$A@4#$EGG3#4$F$
30
29
28
27
26
25
I02E024@N$A@4#$EGG3#4$D
OPJHLQ$
0 0 0
I02E024@N$A@4#$EGG3#4$P
IRQ3
O/H-Q$
I02E024@N$A@4#$EGG3#4$-
W
11
24 23
PRI_239
Power management
...
Bits Name
[31:0] SETENA
Function
Interrupt set-enable bits.
Write:
0 = no effect
1 = enable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
%&'())*+',6)/7)/'8,2(3/4'()4
M87"$2?;B#?#54842E5.6#G25#6$;02E024@$G2#B6$785$"EB6$8$;02E024@$<8B:#N$-.DJJ=$!"#$
24
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
BE9#0$4"#$<8B:#N$4"#$10#84#0$4"#$;02E024@$EG$4"#$7E00#3;E56251$254#00:;4=$,#1234#0$
5
;02E024@$<8B:#$G2#B63$80#$#21"4$A243$926#N$856$5E5.2?;B#?#54#6$BE9.E06#0$A243$0#86$83$
0
0
S#0E$856$215E0#$9024#3=
IRQ2
0
0
0
IRQ1
0
0
0
0
IRQ0
4
3
2
1
0
0
0
0
0
>##$!""#$$%&'()*#(+,-)#./01(234+(-#'%$)#-$(5$%&'(+0646$E5$;81# C.C$GE0$?E0#$25GE0?842E5$
8AE:4$4"#$877#33$4E$4"#$254#00:;4$;02E024@$8008@N$9"27"$;0E<26#3$4"#$3EG4980#$<2#9$EG$4"#$254#00:;4$
12
3.2.2.2 ;02E0242#3=
Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
!"-2#,3.$*4 5676*89(:*800*#,3.$1*#%1%#;%<:
+,The pin the NMI signal is multiplexed
=">'!">?,<%>$,/0 on, must be configured for the NMI function to
generate the non-maskable interrupt request.
!"#$%&'$())*!
'%./.0.(
3.2.2.3 Interrupt channel assignments
The interrupt source assignments are defined in the following table.
K70 Sub-Family Reference Manual, Rev. 2, Dec 2011
Freescale Semiconductor, Inc.
Preliminary
85
Core modules
• Vector number — the value stored on the stack when an interrupt is serviced.
• IRQ number — non-core interrupt source count, which is the vector number minus
16.
The IRQ number is used within ARM's NVIC documentation.
Picking up a IPR
Table 3-4. Interrupt vector assignments
Address
Find the IPR number and byte offset for interrupt m as
follows:
•  the corresponding IPR number, n is given by n = m
DIV 4
•  the byte offset of the required Priority field in this
register is m MOD 4, where:
IRQ1
Vector
NVIC
NVIC
non-IPR
IPR
register register
number number
2
Source module
Source description
3
ARM Core System Handler Vectors
byte offset 0 refers to register bits[7:0]
byte offset 1 refers to register bits[15:8]
byte offset 2 refers to register bits[23:16]
byte offset 3 refers to register bits[31:24].
0x0000_0000
0
–
–
–
ARM core
Initial Stack Pointer
0x0000_0004
1
–
–
–
ARM core
Initial Program Counter
0x0000_0008
2
–
–
–
ARM core
Non-maskable Interrupt (NMI)
0x0000_000C
3
–
–
–
ARM core
Hard Fault
0x0000_0010
4
–
–
–
ARM core
MemManage Fault
0x0000_0014
5
–
–
–
ARM core
Bus Fault
0x0000_0018
6
–
–
–
ARM core
Usage Fault
0x0000_001C
7
–
–
–
—
—
0x0000_0020
8
–
–
–
—
—
0x0000_0024
9
–
–
–
—
—
0x0000_0028
10
–
–
–
—
—
0x0000_002C
11
–
–
–
ARM core
Supervisor call (SVCall)
0x0000_0030
12
–
–
–
ARM core
Debug Monitor
0x0000_0034
13
–
–
–
—
—
0x0000_0038
14
–
–
–
ARM core
Pendable request for system service
(PendableSrvReq)
0x0000_003C
15
–
–
–
ARM core
System tick timer (SysTick)
0x0000_0040
16
0
0
0
DMA
DMA channel 0, 16 transfer complete
0x0000_0044
17
1
0
0
DMA
DMA channel 1, 17 transfer complete
0x0000_0048
18
2
0
0
DMA
DMA channel 2, 18 transfer complete
0x0000_004C
19
3
0
0
DMA
DMA channel 3, 19 transfer complete
0x0000_0050
20
4
0
1
DMA
DMA channel 4, 20 transfer complete
0x0000_0054
21
5
0
1
DMA
DMA channel 5, 21 transfer complete
0x0000_0058
22
6
0
1
DMA
DMA channel 6, 22 transfer complete
0x0000_005C
23
7
0
1
DMA
DMA channel 7, 23 transfer complete
0x0000_0060
24
8
0
2
DMA
DMA channel 8, 24 transfer complete
Non-Core Vectors
13
Chapter 3 Chip Configuration
Table 3-4. Interrupt vector assignments (continued)
Address
Vector
IRQ1
NVIC
NVIC
non-IPR
IPR
register register
number number
2
0x0000_0134
77
61
1
Source module
Source description
3
15
CMP2
—
0x0000_0138
78
62
1
15
FTM0
Single interrupt vector for all sources
0x0000_013C
79
63
1
15
FTM1
Single interrupt vector for all sources
0x0000_0140
80
64
2
16
FTM2
Single interrupt vector for all sources
0x0000_0144
81
65
2
16
CMT
—
0x0000_0148
82
66
2
16
RTC
Alarm interrupt
0x0000_014C
83
67
2
16
RTC
Seconds interrupt
0x0000_0150
84
68
2
17
PIT
Channel 0
0x0000_0154
85
69
2
17
PIT
Channel 1
0x0000_0158
86
70
2
17
PIT
Channel 2
0x0000_015C
87
71
2
17
PIT
Channel 3
0x0000_0160
88
72
2
18
PDB
—
0x0000_0164
89
73
2
18
USB OTG
—
0x0000_0168
90
74
2
18
USB Charger
Detect
—
0x0000_016C
91
75
2
18
Ethernet MAC
IEEE 1588 Timer Interrupt
0x0000_0170
92
76
2
19
Ethernet MAC
Transmit interrupt
0x0000_0174
93
77
2
19
Ethernet MAC
Receive interrupt
0x0000_0178
94
78
2
19
Ethernet MAC
Error and miscellaneous interrupt
0x0000_017C
95
79
2
19
—
—
0x0000_0180
96
80
2
20
SDHC
—
0x0000_0184
97
81
2
20
DAC0
—
0x0000_0188
98
82
2
20
DAC1
—
0x0000_018C
99
83
2
20
TSI
Single interrupt vector for all sources
0x0000_0190
100
84
2
21
MCG
—
0x0000_0194
101
85
2
21
Low Power Timer
—
0x0000_0198
102
86
2
21
—
—
0x0000_019C
103
87
2
21
Port control
module
Pin detect (Port A)
22
Port control
module
Pin detect (Port B)
22
Port control
module
Pin detect (Port C)
0x0000_01A0
104
88
2
0x0000_01A4
105
89
2
14
Table continues on the next page...
K70 Sub-Family Reference Manual, Rev. 2, Dec 2011
Preliminary
86
Freescale Semiconductor, Inc.
Sample code Explained
•  Set up the LPT interrupt:
–  Locate the interrupt vector that you want on the Vector Table list
from the Kinetis device used
• 
Find the NVIC Interrupt Set Enable Register (NVICISERx) for your vector:
• 
Then take the modulo value of your IRQ number by 32 to calculate which bit
to set in the NVICISER2 register
• 
• 
• 
Table continues on the next page...
NVICISER2 for the LPT
85%32 = 21
NVICISER2 |=(1<<21); //Enable LPT interrupts
K70 Sub-Family Reference Manual, Rev. 2, Dec 2011
Freescale Semiconductor, Inc.
15
Preliminary
89
Sample code Explained cont.
# $%&
' ((( the
)NVICICPRx
* +
•  Clear any pending
interrupts
from
:*7 0 :*7:>):7< 3 :*7:!>:7< 3 :*7:*;:7< 2'
–  Use the same!
modulo
result for knowing which bit to set
+ , & -+&-
, &any
-+&-
NVICICPR2|=(1<<21); //Clear
pending
interrupts on
, & .&.//! ! 0
•  Set the interrupt priority writing to the NVICIPx
–  X is the IRQ number
1
–  Just the 4 most2 significant
bits are used ++* *# .
:*73:*7:*;:7<'
:*7
0 :*7:>):7<
3 ++ #
NVICIP85 = 0x30;
//Set Priority
3 to the LPT module
& ! :*7:!>:7< 3 ++ •  Write your ISR
:*7:*;:7< 2'++ .
3
Void lptmr_isr()
{
4 + !
%& LPT0_CSR|=LPT_CSR_TCF_MASK;
//Clear
LPT+
Compare
flag
:*7 :*7:!>:7<' ++> LPTMR0_CSR = ( LPTMR_CSR_TEN_MASK | //enable timer
LPTMR_CSR_TIE_MASK | //enable interrupt
LPTMR_CSR_TCF_MASK );//clear flag
}
16
!"#$%&'()*+%#,-.%#/01*
NVIC Prog Hints
!"#$%%&'&(")#'*+#,-.!.#/0(1&%+2#$#"345+0#(6#63"7'&("2#6(0#89!,#7("'0(:)#&"7:3%&";<
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts !"#$% &'(()*+,-,)./0123405).46)78-*)140264$
*+,-,)302%66/92)140264$)./012340
:%516392340
void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
.+'#'*+#/0&(0&'F#;0(3/&";
void NVIC_EnableIRQ(IRQn_t IRQn)
G"$5:+#!>?"
void NVIC_DisableIRQ(IRQn_t IRQn)
H&2$5:+#!>?"
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
>+'30"#'03+#I!>?A8345+0J#&6#!>?"#&2#/+"%&";
void NVIC_SetPendingIRQ (IRQn_t IRQn)
.+'#!>?"#/+"%&";
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
,:+$0#!>?"#/+"%&";#2'$'32
uint32_t NVIC_GetActive (IRQn_t IRQn)
>+'30"#'*+#!>?#"345+0#(6#'*+#$7'&1+#&"'+003/'
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
.+'#/0&(0&'F#6(0#!>?"
uint32_t NVIC_GetPriority (IRQn_t IRQn)
>+$%#/0&(0&'F#(6#!>?"
>+2+'#'*+#2F2'+4
void NVIC_SystemReset (void)
17 ++
. - - # :*7:>):7<9'
:*7:!>:7<9/' ++
. - - # :*7:*;:7<9%' ++
=
. - - # 18
=*+#&"/3'#/$0$4+'+0#!>?"#&2#'*+#!>?#"345+0)#2++#=$5:+ @ABC#("#/$;+ @A@@D#E(0#4(0+#
&"6(04$'&("#$5(3'#'*+2+#63"7'&("2#2++#'*+#,-.!.#%(734+"'$'&("D

Download Report