Xilinx 7 Series FPGA Power Benchmark Design Summary June 2014 © Copyright 2012 Xilinx © Copyright 2014 Xilinx . Application-centric Benchmarking Process 100G Packet Processor OTN Muxponder ASIC Emulation Wireless Radio & Satellite Modem Edge QAM AVB Switcher Military Radio Mobil Backhaul FPGA resource counts, toggle rates, clock speeds… Xilinx Power Estimator (XPE) version 2014.2 MAX condition used to estimate worst-case static power Competitor’s Estimator XPE © Copyright 2014 Xilinx . Early Power Estimator (EPE) versions 14.0 MAX condition used to estimate worst-case static power Power Benchmark: Traffic Manager in 100G Line Card Virtex-7 X690T FPGA Xilinx Altera Transceiver I/O Dynamic Static 1.35x Interlaken 16 @10.3125G Interlaken 16 @10.3125G Transceivers 20 Interlaken NPU Interlaken 25 Traffic Management 30 Transceivers Total Power (Watts) 35 DDR3 DDR3 DDR3 SDRAM Backplane Interface 15 10 5 Resources 0 Virtex®-7 Stratix V X690T 5SGXA7 -2LE I-Grade Process Tj = 100°C Max 8 x 32-bit DDR3 544 - 1600 Mb/s LC/LEs Flip-Flops Interlaken - 32 10.3 Gb/s Block RAM 15516 Kb DSP Blocks 2 PLLs 8 Interface 622K Environment I/Os GTs Rate Core Freq. *Design results sourced from Xilinx Power Estimator (XPE) version 2014.2 and Altera Early Power Estimator (EPE) version 14.0 Page 3 © Copyright 2014 Xilinx . 232K 167K 250 MHz Total Power (Watts) 30 Transceivers 35 100GE Mapper Transceivers 100G OUT-4 OTL4.10 Optical 10X11.18G Module 100G EFEC Xilinx Altera Transceiver I/O Dynamic Static OTU-4 Framer Power Benchmark: 100GE over OTU4 Transponder Virtex-7 X690T FPGA Overhead Processing 1.31x CAUI 100G OUT-4 Optical Module 100GE Clients 25 Overhead bus 20 15 10 Resources 5 622K 0 Virtex®-7 Stratix V X690T 5SGXA7 -2LE I-Grade Interface I/Os GTs Rate Process Tj = 100°C Max LC / LEs 392K 245K LVCMOS 50 - 250 Mb/s Flip-Flops GT - 10 11.1 Gb/s Block RAM 9,360 Kb GT - 10 10.3 Gb/s Core Freq. 350, 175 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 2014.2 and Altera Early Power Estimator (EPE) version 14.0 Page 4 Environment © Copyright 2014 Xilinx . Power Benchmark: ASIC Prototyping Virtex-7 FPGA 2000T 2.04x 60 Total Power (Watts) 50 40 30 20 10 0 Virtex®-7 Stratix V 2000T EEB (x2) -2LE I-Grade 2 x 952K Resources Interface I/Os GTs 3 64-bit DDR3 366 LVDS 408 © Copyright 2014 Xilinx . Process Tj = 100°C Max Rate LC / LEs - 1066 Mb/s Flip-Flops - 1000 Mb/s Block RAM 21,600 Kb Core Freq. 200 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 2014.2 and Altera Early Power Estimator (EPE) version 14.0 Page 5 Environment 1,224K 765 K Power Benchmark: Wireless WCDMA / LTE Picocell Kintex-7 325T FPGA 64 MB DDR3 OFDM Modulator OFDM Demod DAC DUC / DDC MIMO Modulator 10 MIMO Decoder PCIe 12 QAM DeMod 14 QAM DeMod Total Power (Watts) Layer 1/2 API 1.41x 16 Channel Encoder GbE 18 64 MB DDR3 Channel Encoder Xilinx Altera Transceiver I/O Dynamic Static ADC 8 MicroBlaze™ Processor 6 4 64 MB DDR3 2 Resources 0 Kintex®-7 Stratix V 325T 5SGXA4 -1I -4I Interface 420K I/Os GTs Environment Process Tj = 100°C Max Rate LC / LEs 240K Flip-Flops 150K 3 x 16-bit DDR3 129 - 1066 Mb/s GT - 2 4.0 Gb/s GT - 1 1.25 Gb/s GT - 1 2.5 Gb/s Block RAM DSP Blocks PCIe® Blocks Core Freq. *Design results sourced from Xilinx Power Estimator (XPE) version 2014.2 and Altera Early Power Estimator (EPE) version 14.0 Page 6 © Copyright 2014 Xilinx . 14,562 Kb 342 1 307.2 MHz 14 12 10 Digital Up Converter RRC Filter FIFO J.83 Annex A/B/C Modulator FIFO 16 EMAC Total Power (Watts) 18 10 Gig 1.81x 20 Transceivers 10G Network Interface Dense Edge QAM Modulator Kintex-7 325T FPGA RF 4.6 Gigasample 14-bit DAC DAC IF 128 Channels RF Port #1 8 External External DDR3 DDR3 Memory Memory 6 4 2 0 Kintex®-7 325T -2LE Stratix V 5SGXEA4 -3I 362K Resources Interface Xilinx Altera Transceiver I/O Dynamic Static I/Os GTs LVDS 124 - 1152 Mb/s LVCMOS 12 - 15 MHz 2x 8-bit DDR3 55 - 800 Mb/s - 1 10.3 Gb/s GT Rate Environment Process Tj = 100°C Max LC / LEs 182K Flip-Flops 157K Block RAM DSP Blocks Core Freq. *Design results sourced from Xilinx Power Estimator (XPE) version 2014.2 and Altera Early Power Estimator (EPE) version 14.0 Page 7 © Copyright 2014 Xilinx . 12,402 Kb 641 384, 576,156, 192, 200 MHz Power Benchmark: AVB Switcher Kintex-7 325T FPGA 1.41x Xilinx Altera Transceiver I/O Dynamic Static DDR3 DDR3 DDR3 SDRAM 10 8 SD / HD / 3G Transmit Interface 16SD/HD/3G Inputs1 Frame Buffer Control / Frame Sync 12 Chroma Keyer Mixes, Wipes, Effects 14 SD / HD / 3G Receive Interface Total Power (Watts) 16 8 SD/HD/3G Outputs1 6 4 2 Resources 0 Kintex®-7 325T -2LE (0.9V) Arria V 5AGXB3 I-Grade 362K Environment Process Tj = 100°C Max Interface I/Os GTs Rate LC / LEs 300K 3 x 72-bit DDR3 450 - 800 Mb/s Flip-Flops 188K 2.97 Gb/s Block RAM GT - 16 DSP Blocks Core Freq. *Design results sourced from Xilinx Power Estimator (XPE) version 2014.2 and Altera Early Power Estimator (EPE) version 14.0 Page 8 © Copyright 2014 Xilinx . 10,800 Kb 500 148.5 MHz AVB Switcher (4-channel) Artix-7 100T FPGA DDR 2/3 SDRAM 1.43x SD / HD / 3G Transmit Interface 3 Chroma Keyer Mixes, Wipes, Effects 4 Frame Buffer Control / Frame Sync 4SD/HD/3G Inputs* 4 Total Power (Watts) SD / HD / 3G Receive Interface 5 4 SD/HD/3G Outputs* 3 2 Control Interface 2 *Note: SD/HD/3G inputs and outputs share GTs 1 1 0 Artix®-7 100T -2LE (0.9V) Cyclone V 5CGXC7 C-Grade 149K Xilinx Altera Transceiver I/O Dynamic Static Process Tj = 85°C Max LC / LEs 75K Flip-Flops 47K Block RAM Resources DSP Blocks 2,250 Kb 125 Interface I/Os GTs Rate PLL 1 1 x 64-bit DDR3 112 - 800 Mb/s Phaser Block 1 - 4 2.97 Gb/s Core Freq. GT *Design results sourced from Xilinx Power Estimator (XPE) version 2014.2 and Altera Early Power Estimator (EPE) version 14.0 Page 9 Environment © Copyright 2014 Xilinx . 148.5, 400 MHz Power Benchmark: Single Channel Mobile Backhaul Artix-7 200T FPGA Xilinx Altera Transceiver I/O Dynamic Static 8 Control Plane Processor DDR3 SRAM 1.21x Total Power (Watts) 6 Traffic Management, Packet Processing Modem Timing Synchronization Transceivers Transceivers Ethernet Switch 7 5 4 3 2 1 Resources Arria V 5AGXA5 I-Grade Interfaces 190K 1 x 32-bit DDR3 Tj = 100ºC Max I/Os GTs 72 - Rate 800 Mb/s Flip Flops Block RAM LVDS pairs 128 - 800 Mb/s DSP Blocks SEIO 150 - 100 Mb/s PLL - 4 1.0 Gb/s Core Freq. Switch ports *Design results sourced from Xilinx Power Estimator (XPE) version 2014.2 and Altera Early Power Estimator (EPE) version 14.0 Page 10 Process LC / LEs 0 Artix®-7 200T I-Grade Environment © Copyright 2014 Xilinx . 130K 81K 5,076 Kb 345 2 250, 400 MHz Power Benchmark: Satellite Modem Artix-7 100T FPGA 1.42x 1.42x Total Power (Watts) 1.4 1.2 Xilinx Altera Transceiver I/O Dynamic Static 1.0 0.8 0.6 0.4 0.2 0.0 Artix®-7 Cyclone V 150K 100T 5CGEA7 -2LE (0.9V) I-grade Environment Process Tj = 85°C Max LC/LEs 85 K Flip-Flops 52 K Block RAM Resources Interface DSP Blocks I/Os 1x 32-bit DDR2 69 GTs - Rate 250 Mb/s *Design results sourced from Xilinx Power Estimator (XPE) version 2014.2 and Altera Early Power Estimator (EPE) version 14.0 Page 11 © Copyright 2014 Xilinx . PLLs Core Freq. 3420 Kb 126 2 30, 62.5, 125 MHz Military Network Protocol Platform Data Aggregator Artix-7 200T FPGA Total Power (Watts) 7 1.30x 6 5 4 3 2 1 0 Artix®-7 200T -2LE Arria V 5AGXA5 C-Grade 190K Xilinx Altera Transceiver I/O Dynamic Static Resources Interface I/Os GTs Rate Process Tj = 85°C Max LC / LEs 63K Flip Flops 58K 2x 36-bit RLDRAMs 122 - 520 Mb/s Block RAM GT - 6 5 Gb/s DSP Blocks GT - 8 2.5 Gb/s PCIe® Blocks GT - 1 2.5 Gb/s Core Freq. *Design results sourced from Xilinx Power Estimator (XPE) version 2014.2 and Altera Early Power Estimator (EPE) version 14.0 Page 12 Environment © Copyright 2014 Xilinx . 3600 Kb 400 1 125 MHz
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