GAL Architecture One stage of GAL16V8 in combinational mode The Generic Array Logic device (GAL) is a PAL-type PLD structure comprising a programmable AND array followed by output logic macrocells (OLMC) that provide the versatility. Each OLMC provides a D latch, programmable polarity, output feedback to the fuse array and tri-state output control. One stage of GAL16V8 in registered mode Two-pass logic Example: Y1 = A + B D Q Y2 = A + B + Z Q' Observe that: Y2 = Y1 + Z CPLD Architecture The Altera 3032 is an example of a “Complex Programmable Logic Device” (CPLD). Compared with the GAL structure: – it contains more gates (typically 1000 to 20000) – it has more I/O pins – it is more versatile (much more complex logic equations may be implemented) 1 PAL-like block I/O block I/O block PAL-like block (details not shown) PAL-like block PAL-like block Interconnection wires PAL-like block D Q I/O block I/O block D Q PAL-like block D Q Figure 3.32 Structure of a CPLD Select FPGA Architecture Enable f Flip-flop D A section of a CPLD Figure 3.33 Q 1 The Altera FLEX 10K is an example of a “Field-Programmable Gate Array” (FPGA). Compared with the GAL & CPLD structures: Clock – it contains MANY more gate equivalents (typically > 100 000) – it has more I/O capability – it is based on an highly interconnected array of Look-Up Table (LUT) logic blocks To AND plane Figure 3.29 Output circuitry x1 Logic block Interconnection switches 0/1 I/O block 0/1 f 0/1 0/1 x2 I/O block I/O block (a) Circuit for a two-input LUT x1 x2 f1 0 0 1 1 1 0 0 1 0 1 0 1 (b) f 1 = x 1 x2 + x 1x 2 x1 1 0 f1 0 1 I/O block x2 (c) Storage cell contents in the LUT Figure 3.35 Structure of an FPGA Figure 3.36 A two -input lookup table 2 x1 x2 Select 0/1 0/1 Out 0/1 0/1 f Flip-flop In 1 0/1 In 2 0/1 In 3 D LUT Q Clock 0/1 0/1 x3 Figure 3.37 A three-input LUT Figure 3.38 x3 Inclusion of a flip-flop with a LUT f x1 x1 x2 x2 Figure 3.39 0 0 f 1 0 1 x2 0 1 0 x3 0 f2 f1 0 1 1 f2 1 f A section of a programmed FPGA 3
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