Memory Processing Units
Jaikrishnan Menon, Lorenzo De Carli, VijayraghavanThiruvengadam
Karthikeyan Sankaralingam and Cristian Estan*
UW-Madison and *Google
MPU hardware
MPU
MPU Controller
● Compute fabric (90nm)
o ARM Cortex M3
 250 MHz, 1-issue
 16KB stack, code
o 8 cores / vault
o 128 cores = 1.1W
● MMU can ensure
sequential semantics
3D DRAM stack
MMU
Compute fabric
Scheduler
Buffer
Bank
state
Compute
Scheduler
HMC slice/vault
controller
Programming MPUs
● Shard data among DRAM chips
● CPU-to-MPU memory procedure calls start MPU threads
● MPU-to-MPU continuations

例外(exception）とは何か

New academic calendar for Even Term of 2013

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