All-optical Multiplication Using SOA-MZI based

2010 International Conference on Communication, Computers and Devices, Kharagpur, INDIA December 10-12
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All-optical Multiplication Using SOA-MZI based
Programmable Logic Device (PLD)
Jitendra Nath Roy1, Tanay Chattopadhyay2
Department of Physics
NIT, Agartala West Tripura,
799055, India
1
2
[email protected]
[email protected]
Abstract—Multiplication
is an important task in
computer arithmetic operations. Here, in this paper we
present an all-optical two bit binary multiplier circuit based on
programmable logic device (PLD) with the help of SOA-MZI
(Mach-Zehnder interferometer) based optical tree structured
splitter. This is actually a chip level design. This scheme can
easily and successfully be extended and implemented for any
higher number of input digits.
Keywords- All-optical switch; Mach-Zehnder interferometer;
Programable Logic device; Binary multiplication.
I.
INTRODUCTION
High speed all-optical logic gates are crucial in future highspeed optical networks all-optical signal processing. The
cumbersome, complex and power consuming opticalelectrical-optical (O-E-O) conversion is avoided in all-optical
signal processing. Optical time division multiplexing (OTDM)
technique is one of the promising alternative candidates for the
future all-optical networks. One of the key components in
ultra-fast all-optical OTDM system is SOA-assisted all-optical
switch such as the terahertz optical asymmetric demultiplexer
(TOAD), MZI, UNI etc. SOA-MZI (semiconductor optical
amplifiers on the Mach-Zehnder interferometer arms) devices
are used because they can provide high speeds, low energy
requirement, short latency, high stability, fast switching time,
low switching window (3.5 to 8 ps) and commercial
availability to that of other similar optical time division
multiplexing (OTDM) devices [1-4].
All-optical multiplication has many potential applications
in optical communication and computing systems.
Multiplication is an important task in computer arithmetic
operations. Efficient algorithms and high-speed hardware
should be developed to complete the multiplication.
Multiplication is actually repeated addition. In Binary
multiplication a bit of the multiplier is ANDed with each bit of
the multiplicand in as many levels as there are bits in the
multiplier. The binary output in each level of AND gates are
added in parallel with the partial product of the previous level
to form a new partial product. The last level produces the
product. For ‘j’ multiplier bits and ‘k’ multiplicand bits we
Tamal Sarkar
USIC, University of North Bengal,
Siliguri,
West Bengal, India
need ‘j × k’ AND gates and (j-1) k-bit adders to produce a
product of (j + k) bits. Various logical and arithmetic
operations have been proposed in the field of optical/
optoelectronic computing in last few decades [5-6].
Mukhopadhyay et al. have been proposed all-optical arithmetic
multiplication scheme with nonlinear material [5]. In our
previous paper we proposed an all-optical two by two bit
multiplication with the help of optical half adder and AND gate
based on terahertz optical asymmetric demultiplexer (TOAD)
[7]. In ‘large scale integration’ (LSI) and ‘very large scale
integration’ (VLSI) technology there are hundred and thousand
of logic gates internally interconnected to operate in a
predefined way. Hence, volume of the circuit, power
consumption, quantity production cost and switching time
increases if we combine different logical circuits to built
integrated circuit (IC). To overcome this problem
programmable logic device (PLD) is the best choice, which
replaces large number of logical circuits with a single circuits.
It is ‘programmable’ because we can program it to perform any
logical operation and logical function. In our previous paper we
designed all-optical optical tree structure splitter SOA-MZI
based PLD [8]. In this paper we propose and describe this PLD
to design an integrated circuit that can perform multiplication
of two 2-bit numbers in all-optical domain. It can be
successfully used to design multiplication unit for any higher
bit numbers.
II. ALL- OPTICAL TREE-STRUCTURED SPLITTER BASED
PROGRAMMABLE LOGIC DEVICE WITH THE HELP OF SOA-MZI
INTERFEROMETRIC SWITCH OF USE
PLD consist of a logical AND-array followed by a logical
OR-array. The AND-array generates product of input variables
and OR-array generates sum-of-product (SOP) expressions
[9]. It has M-inputs, n-product terms and N-outputs with
n < 2 M , and can be used to implement a logic function of Mvariables with N-outputs. Normally we can say it 2 M × N
PLD. From fig-1 we see that I 0 , I1 ,L , I M −1 are M-numbers
of inputs to AND-array. The outputs of this AND-array
are P0 , P1 , L , Pn −1 . It can be written as:
Indian Institute of Technology Kharagpur, INDIA
1
2010 International Conference on Communication, Computers and Devices, Kharagpur, INDIA December 10-12
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Pi = ( I 0 ⋅ I 0 ⋅ I1 ⋅ I1 ⋅ L ⋅ I M −1 ⋅ I M −1 ) ; where i = 0 to (n − 1) (1)
And after OR-array the output is:
( n −1) ( M −1)


f k = ∑  ∏ ( I j ⋅ I j ) ; where k = 0 to (N − 1)
i =0  j = 0

(2)
Tree architectures are constructed form tree-structured
splitter and combiner. An ‘active’ 1× N splitter may be
constructed from 2 × 2 switches. One input on each 2 × 2
switch is left unused. Only log 2 N control signals are required
to drive such an active splitter [10].
Figure 2. SOA-based MZI optical switch. 3 dB: 2 × 2 3 dB coupler, IP:
Incoming pulse of wavelength λ1 , CP: control pulse of wavelength λ2 , F:
Band pass filter that blocks CP of wavelength λ2 , ‘A’ and ‘B’ are two inputs.
When A=1 and B=0 light is found at the cross port i.e. cross port output
is AB . When A=B=1 light is found at the bar port i.e. bar port output is AB ,
Pin = incoming pulse power, P× = Cross port power, P = Bar port power.
Figure 1: Tree structured splitter
A 1×16 splitter is shown in Fig-1. Here light beam breaks
at the point Z1 into two portions; again at the points Z2 and Z3
these two beams break into four parts and so on. Using proper
selection of the control input one can send light to any
particular branch. Optical tree-architecture (OTA) with TOAD
based interferometric switch [6] and SOA-MZI based switch
[11] have been proposed to perform logical, arithmetic and
algebraic operations. A.K.Cherri et al proposed all-optical
modified signed digit adder using SOA-MZI OTA [12].
A MZI switch, as shown in Fig-2, is a very powerful
technique to realize ultra- fast switching. In this switch a SOA
is inserted in each arm of an MZI. The pulsed control pulse
(CP) at the wavelength λ2 is split at the first coupler such that
more power passes through one arm. At the same time, the
incoming pulse (IP) at the wavelength λ1 is split equally by
this coupler (C) and propagates simultaneously in the two
arms. In the absence of the λ2 beam, IP exits from the cross
port (lower port in the figure). Its power is P× . However, when
both beams are present simultaneously, all one bits are
directed towards the bar port (upper port in the figure) because
of the refractive-index change induced by the λ2 beam.
Its power is P .The physical mechanism behind the behavior
is cross-phase modulation (XPM). Gain saturation induced by
the λ2 beam reduces carrier density inside one SOA, which in
turn increases the refractive index only in the arm through
which the λ2 beam passes. As a result, an additional π phase
shift can be introduced on the IP beam because of XPM, and
the IP wave is directed towards the bar port during each one
bit. Optical band pass filters (F) are placed in front of the
output ports for blocking the original λ2 signal. The MZI
scheme is preferable over cross-gain saturation as it does not
reverse the bit pattern and results in a higher on–off contrast
simply because nothing exits from the bar port during 0 bits
[13]. The logical expression of bar and cross port output can
be expressed as AB and AB .
In this present literature SOA-MZI based optical treestructured splitter (OT-SS) is used to design 1×16 AND-array
of 16 × 2 PLD (PROM). Here, log 2 16 = 4 control signals
(‘A’, ‘B’, ‘C’ and ‘D’) and ( 2log2 16 − 1) = 15 numbers of SOA-
MZI switches are placed at the position of Z1, Z2, Z3, Z4, Z5,
Z6, Z7, Z8, Z9, Z10, Z11, Z12, Z13, Z14 and Z15 respectively.
Hence the logical outputs of port-1 to port-16 as ABCD ,
ABCD , ABCD , ABCD , ABCD , ABCD , ABCD , ABCD ,
ABCD , ABCD , ABCD , ABCD , ABCD , ABCD , ABCD
an ABCD respectively.
Figure 3: Output of SOA-MZI switch as the function of control pulse (CP).
Here output is taken from the cross port. When CP =1, then cross port takes
the value of ‘Pin’. When CP=0 then cross port takes the value zero (0).
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2010 International Conference on Communication, Computers and Devices, Kharagpur, INDIA December 10-12
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Figure 4: SOA-MZI based OT-SS for AND array.
When CP is absent then input data pulse (IP) comes out to
the bar port and when CP is present then IP is present at the
cross-port. Hence controlling the CP of SOA-MZI switch we
can disconnect an incoming data to the output. The schematic
diagram of this type of operation is shown in the Fig-3.
any of port-1 to port-16 (AND-array output) to the beam
combiner as shown in the fig-5. The combined beam is the
final output. Ei, Fi, Gi, Hi, Ii, Ji, Ki, Li, Mi, Ni, Oi, Pi, Qi, Ri, Si,
Ti are the programming inputs respectively (where i = 1 to (N1) for 2 M × N PLD). According to our designed 16 × 2 PLD
(PROM) of fig-7, we require two sets of 16-programming
inputs viz. {E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0,
S0, T0 } for one outputs f 0 respectively.
III.
TWO BIT MULTIPLICATION UNIT
Any logical functions can be performed using this PLD
(PROM). Two bit multiplier is designed here. This process can
be successfully used for designing multiplication unit for
higher bits. Consider the two bit adder,
A B
× C D
f 0 f1 f 2 f3
The truth table of the two bit multiplier is shown in Table-I.
From this table we found
f 0 = ( ABCD )
f1 = ( ABCD + ABCD + ABCD )
f 2 = ( ABCD + ABCD + ABCD + ABCD + ABCD + ABCD )
Figure 5: All optical circuit for PROM. BC: beam combiner
So, CP of the SOA-MZI can be successfully used as
programming input, by which we can connect or disconnect
f 3 = ( ABCD + ABCD + ABCD + ABCD )
We use 16 × 4 PLD (PROM) to perform this operation. The
circuit is shown in the fig-6.
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2010 International Conference on Communication, Computers and Devices, Kharagpur, INDIA December 10-12
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Hence programming inputs should be
{E0 F0 G0 H0 I0 J0 K0 L0 M0 N0 O0 P0 Q0 R0 S0 T0} ={1 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0}; {E1 F1 G1 H1 I1 J1 K1 L1 M1 N1 O1 P1
Q1 R1 S1 T1} = {0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0}; {E2 F2 G2 H2
I2 J2 K2 L2 M2 N2 O2 P2 Q2 R2 S2 T2} = {0 1 1 0 1 1 1 0 1 0 0 0
0 0 0 0} and {E3 F3 G3 H3 I3 J3 K3 L3 M3 N3 O3 P3 Q3 R3 S3 T3}
= {1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0}.
TABLE I.
TRUTH TABLE OF TWO INPUT MULTIPLER
Inputs
IV.
CONCLUSSION
In this paper we have reported a novel design of SOA-MZI
PLD based multiplication. Here, in this proposed scheme the
significant advantage is that the proposed multiplication unit
can perform multiplication operations, which are ultra-high
speed all-optical in nature. This scheme can easily and
successfully be extended and implemented for any higher
number of input digits.
REFERENCES
Outputs
A
B
C
D
f0
f1
f2
f3
0
0
0
0
0
0
0
0
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0
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1
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1
1
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0
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1
1
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1
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0
0
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0
0
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0
1
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1
0
0
1
0
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1
0
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1
0
1
1
0
1
1
0
0
0
0
0
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1
1
0
1
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1
1
1
1
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0
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0
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1
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1
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0
0
1
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Figure 6: Two-bit multiplier using SOA-MZI based PLD (PROM)
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