0081.Using DAC NCO to solve LO fractional spur problem

Using DAC NCO to solve LO fractional spur problem
Decapton Wang
ABSTRACT
High speed Digital-to-Analog Converter (DAC) and Local Oscillator (LO) products are
widely used in wireless communication applications. In a typical transmitter, the modulator
mixes IF product and LO product to generate RF output. Usually, the LO works under
fractional mode to realize various frequency plans flexibly. However, LO under such mode
have fractional spur and integer boundary spur problems. Such spurs may deteriorate
EVM and ACPR at modulator output. Although there are some ways like dither that can
suppress fractional spur and integer boundary spur, such ways sacrifice LO phase noise
performance. So it is hard for designers to optimize both phase noise and spur
performance at the same time. This application note introduces a method that uses NCO
in high speed DAC to compensate fractional part of LO frequency. With this method, LO
can work under integer mode and designers can focus only on optimizing LO phase noise
without caring about the spur problem. And therefore both spur and phase noise problems
in fractional LO can be solved.
Contents
1
Definition....................................................................................................................................... 2
2
Spur problem in fractional PLL ................................................................................................... 2
3
Using DAC NCO to compensate fractional part of LO frequency ............................................. 4
4
Application examples................................................................................................................... 7
5
Conclusion.................................................................................................................................... 9
References............................................................................................................................................ 9
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figures
Typical fractional PLL structure ..................................................................................... 2
Fractional spurs under PLL without/with dither ............................................................ 3
Integer boundary spurs under different PFD frequencies ............................................ 3
Influence of integer boundary spur ................................................................................ 3
ACPR degradation caused by integer boundary spur .................................................. 4
Typical NCO structure ..................................................................................................... 5
Typical complex TX path ................................................................................................. 6
Test-bench used in this work.......................................................................................... 7
WCDMA pattern signal ACPR test results ..................................................................... 8
Table 1.
Table 2.
Table 3.
Tables
Detailed EVM information used in this work .................................................................. 7
Frequency plans for fractional LO and integer LO ........................................................ 7
WCDMA pattern signal ACPR test summary ................................................................. 9
1
1
Definition
IBS: Integer boundary spur
EVM: Error vector Magnitude or Evaluation Module, depending on the context.
NCO: Numerical controlled oscillator
LO: Local oscillator
TX: Transmitter
2
Spur problem in fractional PLL
Figure 1 shows a typical fractional PLL structure. The output frequency can be derived as
f PFD  f REF / R
f LO  f PFD * ( N 
Reference input
R
N+DEN/NUM
PFD
&
CP
(1)
DEN
)
NUM
LPF
Output
DEN, NUM
Sigma Delta modulator
Figure 1.
Typical fractional PLL structure
PLL under fractional mode will generate two kinds of spurs, fractional spur and integer boundary
spur. The fractional spurs locate at
f fractional _ spur 
f PFD * k
,k  1,2,...
NUM
(2)
The integer boundary spur (IBS) locates at
f int eger _ boundary _ spur 
f PFD * DEN
NUM
(3)
According to equation (2) and (3), the IBS belongs to fractional spur. But there is difference
between the two. The fractional spur can be suppressed by dither while the IBS can not, as
Figure 2 shows. Usually, designers need to adjust PFD frequency to suppress IBS. An
experience is making the fractional-N part (DEN/NUM) as close as 0.5. Figure 3 shows integer
boundary spurs under different PFD frequencies.
2 Using DAC NCO to solve LO fractional spur problem
Figure 2.
Figure 3.
Fractional spurs under PLL without/with dither
Integer boundary spurs under different PFD frequencies
Fractional spur can deteriorate system EVM and ACPR. In wideband application, it may
generate in-band product and harm EVM and ACPR. In narrow band application, it may
generate close-in product and harm ACPR. Figure 4 shows the influence of fractional spur.
Figure 5 provides an actual WCDMA single carrier test result to show how ACPR in modulator
output is degraded by LO fractional spur.
Figure 4.
Influence of integer boundary spur
Using DAC NCO to solve LO fractional spur problem 3
* RBW 30 kHz
* VBW 300 kHz
Ref
-13.5 dBm
* Att
5 dB
* SWT 2 s
-20
IF: 103.36M, RF: 2605M
LO: 2708.36M, PFD: 122.88M
Integer boundary spur: 5M
-30
-40
1 RM *
A
-50
CLRWR
-60
-70
-80
NOR
-90
-100
3DB
-110
Tx Channel
Bandwidth
W-CDMA 4.096 FWD
4.096 MHz
Adjacent Channel
Bandwidth
Spacing
Alternate Channel
Bandwidth
Spacing
Figure 5.
4.096 MHz
5 MHz
4.096 MHz
10 MHz
Power
-12.02 dBm
Lower
Upper
-64.71 dB
-64.61 dB
Lower
Upper
-76.28 dB
-74.49 dB
ACPR degradation caused by integer boundary spur
Traditionally, designers use two ways to suppress fractional spurs. For the non-IBS, it can be
suppressed by dither, as Figure 2 shows. But dither introduces new phase noise especially at
close-in region. Take Figure 2 as an example, the close-in phase noise (within 100KHz offset) is
increased about 1~2dB by dither. For the IBS, it can be suppressed by adjusting PFD frequency
and making
the product of NUM/DEM as close as 0.5. However, such way has the probability to
Date: 31.OCT.2013 13:42:58
decrease PLL loop bandwidth and then cause VCO phase noise pushes into close-in region.
Therefore, the LO output close-in phase noise increases, as the left side of Figure 3 shows.
According to the above analysis, it is hard for a fractional PLL to provide both good phase noise
and spur performance at the same time. A method is needed to solve fractional spur problem
without sacrificing phase noise performance.
3
Using DAC NCO to compensate fractional part of LO frequency
In this section, a method using DAC NCO is introduced to solve fractional spur problem. First of
all, the LO frequency can be written as
f LO  f LO_fractional  f LO_integer
(4)
All the fractional spurs are from LO fractional part. If the fractional part can combine with IF, the
LO will work under integer mode without fractional spur problem, as equation (5) shows. The
problems are whether there is hardware resource to realize it in TX path and whether such
hardware introduces higher spurious products compared to those in fractional LO.
f IF  f IF _ initial  f LO _ fractional
4 Using DAC NCO to solve LO fractional spur problem
(5)
In TX, the Numerical Controlled Oscillator (NCO) can realize frequency transform. There are two
NCOs in TX. The first one is FPGA, and the other one is DAC. This note focuses on DAC NCO
and illustrates how to use DAC NCO to solve fractional LO spur problem.
An NCO is used to generate sine and/or cosine wave in digital domain. It consists from
frequency and phase registers, phase accumulator (PA), dither generator and phase-amplitude
converter (PAC), as Figure 6 shows [1] [2]. Equation (6) derives the NCO transfer function. The
TS and fS are period and frequency of NCO operating clock. fNCO is the target frequency. ΦOFFSET
and ΦDITHER are optional phase offset and phase dither, separately.
[
Frequency
Register
f
[ NCO 2 N ]
fS
N
+
f NCO N
2 ]* n
fS
-1
Z
Phase Accumulator
NPA1
NPA2
+
+
ND
Phase
Register
Dither
Generator
sin
cos
Look-Up Table
Phase-Amplitude Converter
NP
Figure 6.
M
NPHASE
M
f
  [ NCO 2 N ] * n+OFFSET  DITHER
fS
Typical NCO structure
yNCO  sin 2 * ( nTs* f NCO   )
f
 sin 2 * ( n* NCO  OFFSET  DITHER )
fS
(6)
To initiate NCO, users need to transform the target frequency to frequency word and then write it
to frequency register. In digital domain, the target frequency should be normalized to fNCO/fS and
then be quantized to N bit. So the frequency word can be written as
Freq _ word  [
f NCO N
2 ]
fS
(7)
The symbol “[ ]” means rounding the number to its nearest integer number. The integer
frequency word enters PA and accumulates to an inter-mediate phase.
N PA1  [
f NCO N
2 ]* n,
fS
(8)
n  1,2,3...
Usually, there are optional phase offset and phase dither in NCO, and the final phase can be
derived as
N PHASE  [
f NCO N
2 ]* n+OFFSET +DITHER ,
fS
(9)
n  1,2,3...
Using DAC NCO to solve LO fractional spur problem 5
The final phase information is sent to PAC. The PAC is a look-up table that can translate phase
information to amplitude. And after this step, users can get digital sine and/or cosine wave as
equation (5) shows.
The NCO accuracy is measured in two parts, frequency resolution and spur. The relative
frequency resolution is 1/2^N, and the absolute frequency resolution is fS/2^N. Take
DAC34SH84 as an example, its N is 32. When fS is 1.5GHz, the absolute frequency resolution is
0.35Hz (1.5G/2^32). This resolution is so small that it can meet most of wireless infrastructure
applications’ need.
The NCO spur is introduced by truncation operations. For saving hardware resource, there are
phase truncation and amplitude truncation in NCO. The phase truncation occurs in phase
forming path. The NPA1, NPA2 and NPHASE are all truncation products of their previous stages. The
amplitude truncation occurs in PAC, and it is introduced by the truncated PAC output. The
truncation operations, whatever phase or amplitude, introduce spurious products [2]. Without
dither, the truncation spur level can be estimated as the larger one between -6NPHASE and -6M
[3]. For further improving NCO spur performance, dither is usually used. Dither is a series of
pseudo-random numbers. In spectrum, it can be treated as wide band white noise. Added to the
PAC input, it can randomize the truncation error from NPA1 to NPHASE. So the truncation spur can
be split to noise floor, and then the SFDR performance improves [1][2].
In the modern state-of-art DAC designs, dither is usually removed for saving more hardware
resource and getting lower noise floor. Then the NCO spur performance is dominated by NPHASE
and M. Take DAC34SH84 as an example, NPHASE and M are all 16. After optimization, its NCO
spur level can be smaller than -90dBc. Compared to LO fractional spurs, the NCO spur is much
lower, so it can be used to compensate LO fractional part without introducing larger spurs.
In application, designers also need to note that the NCO in DAC can realize complex upconversion but cannot realize real up-conversion. Figure 7 shows the detailed complex TX path.
The NCO discussed above is used in complex digital mixer in DAC, as equation (10) and (11)
show. If using real up-conversion, designer needs to use NCO in FPGA rather than DAC.
Digital mixer
Iout(t)
Iin(t)
DAC core
0
RFout
90
Qin(t)
DAC core
cosine
sine
Modulator
Qout(t)
NCO
DAC
Figure 7.
LO
Typical complex TX path
I OUT  I in cos IF  j Qin sin IF
QOUT   I in sin IF  jQin cos IF
6 Using DAC NCO to solve LO fractional spur problem
(10)
RFout  I out *cos RF  Qout *sin RF
(11)
 I in *cos(IF  RF )  j Qin *cos(IF  RF )
4
Application examples
This section introduces an application example to show to how to use DAC NCO to compensate
LO fractional part. The test-bench consists from TSW1400 EVM, TSW30SH84 EVM and an LO
source, as Figure 8 shows [4][5][6]. Detailed EVM information is listed in table 1.
Table 1.
Detailed EVM information used in this work
Part number
Information
TSW30SH84 EVM
Complete RF signal chain evaluation module including DAC34SH84 and TRF3705
LMX2581 EVM
Evaluation module for wideband frequency synthesizer with integrated VCO
TSW1400 EVM
High Speed Data Capture and Pattern Generation Platform
TSW1400 EVM
Pattern signal generator
LO source
TRF3705
Modulator
DAC34SH84
TX DAC
TRF3705
Modulator
TSW30SH84 EVM
Figure 8.
Test-bench used in this work
Below steps illustrate the detailed compensation process.
1. The initial frequency plan is listed in the upper side of table 2. The dominant fractional spur is
IBS that lies at 5MHz offset of LO and causes ACPR degradation. For cancelling the IBS, LO
should work under integer mode, and its frequency should change to 2703.36M. Therefore IF
changes to 98.36M, as the bottom side of table 2 shows.
Table 2.
Frequency plans for fractional LO and integer LO
Fractional LO frequency plan
DAC clock, MSPS
IF, MHz
RF, MHz
LO, MHz
PFD, MHz
Dominant fractional spur, MHz offset
1228.8
103.36
2605
2708.36
122.88
5
Integer LO frequency plan
DAC clock, MSPS
IF, MHz
RF, MHz
LO, MHz
PFD, MHz
Dominant fractional spur, MHz offset
1228.8
98.36
2605
2703.36
122.88
No fractional spur
Using DAC NCO to solve LO fractional spur problem 7
2. Suppose the IF from FPGA to DAC is zero, then all the frequency up-conversion is done in
DAC. The NCO frequency word length of DAC34SH84 is 32 bit. fNCO equals to 98.36M.
According to equation (6), the frequency word is
Freq _ word  [
f NCO N
98.36 32
2 ][
2 ]  343793118
f DAC
1228.8
(12)
Change the decimal value to hex and write it into DAC34SH84
(343793118)2  (147 DDDDE) 16
(13)
3. Set the LO frequency to 2703.36M.
4. Send single carrier WCDMA pattern signal and four carrier WCDMA pattern signal from
FPGA (TSW1400) to DAC (DAC34SH84), and capture the modulator (TRF3705) output.
* RBW 30 kHz
* RBW 30 kHz
* VBW 300 kHz
Ref
-13.5 dBm
* Att
5 dB
* VBW 300 kHz
* SWT 2 s
Ref
-20
* Att
5 dB
A
-30
-40
A
-40
1 RM *
-50
CLRWR
CLRWR
-60
-50
-60
-70
-70
-80
NOR
NOR
-80
-90
-90
-100
-100
3DB
-110
3DB
-110
Tx Channel
Bandwidth
W-CDMA 4.096 FWD
4.096 MHz
Adjacent Channel
Bandwidth
4.096 MHz
Spacing
5 MHz
Alternate Channel
Bandwidth
4.096 MHz
Spacing
10 MHz
Tx Channel
Bandwidth
W-CDMA 4.096 FWD
Power
-12.02 dBm
Lower
Upper
-64.71 dB
-64.61 dB
Adjacent Channel
Lower
Upper
-76.28 dB
-74.49 dB
Alternate Channel
Bandwidth
4.096 MHz
Bandwidth
4.096 MHz
Spacing
5 MHz
Spacing
4.096 MHz
10 MHz
* Att
5 dB
Ref
* SWT 2 s
A
-40
CLRWR
-50
Lower
Upper
-78.30 dB
-76.54 dB
-19.4 dBm
* Att
5 dB
* SWT 2 s
A
-40
1 RM *
-60
CLRWR
-50
-60
-70
-70
Date: 31.OCT.2013
-80
13:42:58
-80
Date: 31.OCT.2013
NOR
-90
13:59:02
NOR
-90
-100
-100
3DB
-110
Standard: W-CDMA 4.096 FWD
Adjacent Channel
Tx Channels
Lower
Upper
Ch1
-72.95 dB
-72.75 dB
-20
-30
-20
-30
1 RM *
-12.28 dBm
Lower
Upper
* VBW 300 kHz
* VBW 300 kHz
-19.1 dBm
Power
* RBW 30 kHz
* RBW 30 kHz
Ref
* SWT 2 s
-20
-30
1 RM *
-12 dBm
(Ref)
-20.29 dBm
Alternate Channel
Standard: W-CDMA 4.096 FWD
Adjacent Channel
Tx Channels
Lower
Upper
Ch1
(Ref)
-20.45 dBm
Ch2
-20.34 dBm
Ch3
-20.34 dBm
-20.04 dBm
Ch4
-20.40 dBm
-14.11 dBm
Total
-14.36 dBm
Ch2
-20.16 dBm
Ch3
-20.05 dBm
Ch4
Total
Figure 9.
Date: 31.OCT.2013
-63.03 dB
-63.17 dB
3DB
-110
Lower
Upper
-67.61 dB
-68.08 dB
WCDMA pattern signal ACPR test results
14:14:54
8 Using DAC NCO to solve LO fractional spur problem
Date: 31.OCT.2013
14:16:19
-67.78 dB
-66.74 dB
Alternate Channel
Lower
Upper
-68.50 dB
-67.84 dB
Table 3.
WCDMA pattern signal ACPR test summary
Single carrier ACPR
(adjacent channel, dBc)
Four carrier ACPR
(adjacent channel, dBc)
Fractional LO
Integer LO
-64.61
-72.75
-63.03
-66.74
According to Table 3, the adjacent channel power suppression improves after using DAC NCO
to compensate LO fractional part. Designers can also use similar steps in application.
5
Conclusion
This application notes discusses the influence of LO fractional spur on TX and how to use DAC
NCO to cancel it. The fractional spur deteriorates TX EVM and ACPR. It can be suppressed with
the sacrifice of increasing LO phase noise. The NCO is introduced to solve this problem.
According to analysis and test results, the spur level of NCO is much lower than that of fractional
LO. It can be used to compensate LO fractional part without introducing higher spurious product.
Designers can use this method to make the LO work under integer mode and focus only on
optimizing LO phase noise performance.
References
1.
2.
3.
4.
5.
6.
GC5316 datasheet. Texas Instruments Inc., 2004 (SLWS154A)
Analysis of Fixed-Point Numerically Controlled Oscillator, MathWorks
The NCO as a Stable, Accurate Synthesizer, Intersil, 1998 (TB318.1)
DAC34SH84 datasheet, Texas Instruments Inc., 2012 (SLAS808D)
TSW30SH84 EVM User's Guide, Texas Instruments Inc., 2012 (SLAU433)
TSW140x High Speed Data Capture/Pattern Generator Card, Texas Instruments Inc., 2012
(SLWU079A)
Using DAC NCO to solve LO fractional spur problem 9

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