ECE 697 Delta-Sigma Converters Design
Lecture#16 Slides
Vishal Saxena
([email protected])
© Vishal Saxena
CIFF Example 1








CIFF, order = 4
All NTF zeros at z=1, i.e. opt =0.
OBG = 3, OSR = 16, nLev = 15.
Low-distortion topology
 b(1) =b(5)= 1
 b(2:4)=0
a = [2.1 1.9 0.86 0.16]
b = [1 0 0 0 1]
c = [1 1 1 1]
g = [0 0]
NTF(z)
STF(z)
1
1
0.5
0.5
0
0
-0.5
-0.5
-1
-1
-0.5
0
0.5
1
-1
-1
-0.5
L0(z)
1
0.5
0.5
0
0
-0.5
-0.5
-1
-0.5
0
File: CIFB_4th_Order_1.m
© Vishal Saxena
0.5
1
0.5
1
L1(z)
1
-1
0
0.5
1
-1
-1
-0.5
0
CIFF Example 1 contd. : NTF and STF
50
3
NTF
STF
NTF
STF
2.5
0
2
Mag, dB
Mag
-50
1.5
-100
1
-150
0.5
0
0
0.1
0.2
0.3
0.4
0.5
/
0.6
0.7
0.8
0.9
1
-200
0
0.1
0.2
0.3
0.4
0.5
/
File: CIFF_4th_Order_1.m
© Vishal Saxena
0.6
0.7
0.8
0.9
1
CIFF Example 1 contd. : Loop-Filter States
Transient Simulation
Integrator States
10
6
u
v
8
x1
x2
x3
x4
4
6
4
2
2
0
0
-2
-2
-4
-6
-4
-8
-10
0
100
200
300
400
500
600
samples, n
700
800
900
1000
-6
0
100
File: CIFF_4th_Order_1.m
© Vishal Saxena
200
300
400
500
600
samples, n
700
800
900
1000
CIFF Example 1 contd. : Simulated Spectrum
Modulator Output Spectrum
0
-20
-40
-60
dBFS
-80
-100
-120
-140
SNDR = 80.4 dB
ENOB = 13.06 bits
@OSR = 16
-160
-180
-200
0
0.1
0.2
0.3
0.4
0.5
0.6
/
File: CIFF_4th_Order_1.m
© Vishal Saxena
0.7
0.8
0.9
1
CIFF Example 2








CIFF, order = 4
All NTF zeros at z=1, i.e. opt =0.
OBG = 3, OSR = 16, nLev = 15.
Only single input feed-in used
 b(2:end)=0
a = [2.1 1.9 0.86 0.16]
b = [1 0 0 0 0]
c = [1 1 1 1]
g = [0 0]
NTF(z)
STF(z)
1
1
0.5
0.5
0
0
-0.5
-0.5
-1
-1
-0.5
0
0.5
1
-1
-1
-0.5
L0(z)
1
0.5
0.5
0
0
-0.5
-0.5
-1
-0.5
0
File: CIFB_4th_Order_2.m
© Vishal Saxena
0.5
1
0.5
1
L1(z)
1
-1
0
0.5
1
-1
-1
-0.5
0
CIFF Example 2 contd. : NTF and STF
50
3.5
NTF
STF
NTF
STF
3
0
2.5
-50
Mag
Mag, dB
2
1.5
-100
1
-150
0.5
0
0
0.1
0.2
0.3
0.4
0.5
/ 
0.6
0.7
0.8
0.9
1
-200
0
0.1
0.2
0.3
0.4
0.5
/
 Notice the significant STF peaking !
File: CIFF_4th_Order_2.m
© Vishal Saxena
0.6
0.7
0.8
0.9
1
CIFF Example 2 contd. : Loop-Filter States
Transient Simulation
Integrator States
10
50
u
v
8
6
30
4
20
2
10
0
0
-2
-10
-4
-20
-6
-30
-8
-40
-10
0
100
200
300
400
500
600
samples, n
700
800
900
1000
x1
x2
x3
x4
40
-50
0
100
200
300
400
500
600
samples, n
700
 Last integrator output has significant signal content
 Use dynamic range scaling.
 Last integrator will burn more power in this case.
File: CIFF_4th_Order_2.m
© Vishal Saxena
800
900
1000
CIFF Example 2 contd. : Simulated Spectrum
Modulator Output Spectrum
0
-20
-40
-60
dBFS
-80
-100
-120
-140
SNDR = 82.1 dB
ENOB = 13.34 bits
@OSR = 16
-160
-180
-200
0
0.1
0.2
0.3
0.4
0.5
/
0.6
File: CIFF_4th_Order_2.m
© Vishal Saxena
0.7
0.8
0.9
1
Other Examples of Feed-forward Topologies
 Low-distortion CRFF topology
 CRFF_4th_Order_1.m
 CRFF with single feed-in
 CRFF_4th_Order_2.m
 Low-distortion CIFF topology with optimized NTF zeros
 CIFF_Opt_4th_Order_1.m
 CIFF with single feed-in and optimized NTF zeros
 CIFF_Opt_4th_Order_2.m
 STF peaking in FF topologies with single feed-in is an issue
 CT FF DSM will have STF peaking as full-feedforward branch can’t be used.
 The feed-in coefficients b’s can be strategically used to realize CIFF/CRFB
topology with better out-of-band STF attenuation.
© Vishal Saxena
L-0 Cascade Simulation
 TBD
File: TBD.m
© Vishal Saxena

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