Using XILINX ISE DESIGN SUITE 14.7 WebPack create the following PlanAhead projects
targeting a specific FPGA device located on the Nexys2 board.
Modeling Arithmetic Logic Unit (ALU)
Task1: Design a 3-bit ALU which performs the next operations:
Logical operations:
F0 = A
F1 = B
F2 = 1
F3 = 0
F4 = A
F5 = B
F6 = A⋅ B
F7 = A+B
F8 = A ⊕ B
F9 = A⊙ B
F10 = A⋅ B
F11= A+ B
F12= A ⋅ B
F13= A⋅ B
F14= A + B
F15= A + B
Arithmetic operations:
F0 = A plus B
F1 = A plus A
F2 = (A+B) plus A
Implement the design and verify the functionality in hardware.

Ege Gulcan - CESCA

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