View Abstract - Circuit Cellar

CHIMAERA - The Poly-Magneto-Phonic Theremin An Expressive Touch-Less Hall-Effect Sensor Array
WIZnet Connect The Magic Design Challenge
Registration Number WZ1256
July 27, 2014
Abstract
The Chimaera is a touch-less, expressive, polyphonic and electronic music controller based on
magnetic field sensing. An array of linear hall-effect sensors and their vicinity make up a continuous 2D interaction space. The sensors are excited with Neodymium magnets worn on fingers. The
device continuously tracks position and vicinity of multiple present magnets along the sensor array
to produce event signals accordingly. Apart from the two positional signals, an event also carries
the magnetic field polarization, a unique identifier and group association. We like to think of it as a
mixed analog/digital offspring of theremin and trautonium. These general-purpose event signals
are transmitted and eventually translated to musical events according to custom mappings on a
host system.
With its touch-less control (no friction), high update rates (2-4kHz), its quasi-continuous spatial
resolution and its low-latency (<1 ms), the Chimaera can react to most subtle motions instantaneously and allows for a highly dynamic and expressive play. Its open source design additionally
gives the user all possibilities to further tune hardware and firmware to his or her needs. The Chimaera is network-oriented and configured with and communicated by Open Sound Control, which
makes it straight-forward to integrate into any setup.
The hardware of the Chimaera consists of two types of printed circuit boards and an enclosure.
Multiple sensor units are daisy-chained to form the sensor array and connected to a single digital
signal processing (DSP) unit.
A single sensor unit consists of 16 linear hall-effect sensors spaced 5mm apart and routed to
a single output through a 16:1 multiplexer which is switched by the DSP unit. Downstream the
multiplexer, the analog signal runs through an amplification circuitry.
The DSP unit is a mixed-signal board and handles sensor read out, event detection and host communication. It is based on an STM32F303Cx ARM Cortex M4 microcontroller in combination with
WIZnet W5500, a hardwired 100Mbit IPv4/PHY chip taking care of all low-level networking protocols via UDP/TCP. The boards analog part features 10 analog inputs providing connection points for
the sensor units, leading to a maximally possible array of 160 sensors. Those analog inputs connect
directly to three in parallel running 12bit analog-to-digital converters.
Networking technology in a zero configuration setup has advantages in respect to long-distance
transmission, operating system independence and inherent ability for network performances. We
thus use the Open Sound Control (OSC) specification via UDP/TCP as low-level communication layer.
1
1
Images
2
3
2
Block diagram
4
(1 − 10)×
Sensor unit
16× Linear hall effect sensors
16:1 Analog multiplexer
OpAmp circuitry
+
1×
Digital signal processing unit
STM32F303Cx: ARM Cortex M4 @72 MHz
WIZnet W5500: in-silico UDP/TCP/IPv4 stack
3× 12-bit ADCs
⇓
Linear hall-effect sensor array
−500
⇓
A modular hardware design consisting of identical sensor units and a single DSP unit embedded in a wooden case
allows building devices with array sizes of 16-160 sensors.
Sensor dump
⇓
Areas of interest
⇓
Sensor calibration
⇒ Sensor value normalization
⇓
m
Blob detection
⇓
Magnet calibration ⇒ Vicinity estimation
⇓
Polynomial blob interpolation
⇓
Blob tracking over space and time
⇓
Event data generation
(position Xi , vicinity Yi , polarity Pi , group Gi )
The firmware generates ON, OFF and SET events per blob out of a raw sensor dump whereby vicinity - magnetic field
relationship of permanent magnets and differences in sensor sensitivity are taken into account with a precedent two-step
calibration.
(Chimaera)
Client side
Deconstruction of event data (X1 , Y1 , P1 , G1 ), . . . , (Xn , Yn , Pn , Gn )
⇓
Serialization to Open Sound Control (e.g. TUIO, MIDI)
⇓
Transmission via wired IPv4 UDP/TCP
⇓
Deserialization from Open Sound Control
⇓
Reconstruction of event data (X1 , Y1 , P1 , G1 ), . . . , (Xn , Yn , Pn , Gn )
Host side
(Interpreter: e.g. SuperCollider, Pure Data, MIDI, MAX/MSP, . . . )
Event data can be packed into custom higher layer specifications
on top of OSC, depending on the usage scenario. Time
5
synchronization between host and device is based on the precision time protocol (PTPv2).
3
Code snippet
Asynchronous function implementations for UDP sending from the driver for the WIZnet W5500 chip.
CCM TEXT
uint fast8 t
udp send nonblocking ( u i n t 8 t sock , u i n t 8 t ∗o buf , u i n t 1 6 t l e n )
{
i f ( ( l e n == 0 ) | | ( l e n > CHIMAERA BUFSIZE + WIZ SEND OFFSET + 3 ) )
ret urn 0 ;
u i n t 8 t ∗tmp buf o = o b u f + WIZ SEND OFFSET ;
u i n t 1 6 t p t r = Sn Tx WR [ sock ] ;
w i z j o b a d d ( ptr , len , tmp buf o , NULL , W 5 5 0 0 s o c k e t s e l [ sock ] . t x b u f , WIZ TX ) ;
p t r += l e n ;
Sn Tx WR [ sock ] = p t r ;
uint8 t
flag [0]
flag [1]
wiz job
∗ f l a g = tmp buf o + l e n ;
= p t r >> 8 ;
= p t r & 0 xFF ;
a d d ( WIZ Sn TX WR , 2 , &f l a g [ 0 ] , NULL , W 5 5 0 0 s o c k e t s e l [ sock ] . reg , WIZ TX ) ;
// send data
f l a g [ 2 ] = WIZ Sn CR SEND ;
w i z j o b a d d ( WIZ Sn CR , 1 , &f l a g [ 2 ] , NULL , W 5 5 0 0 s o c k e t s e l [ sock ] . reg , WIZ TX ) ;
wiz job run nonblocking ( ) ;
re turn 1 ;
}
void
CCM TEXT
ud p se nd bl ock ( u i n t 8 t sock )
{
wiz job run block ( ) ;
uint8 t ir ;
uint8 t flag ;
do
{
dma read sock ( sock , WIZ Sn IR , &i r , 1 ) ;
i f ( i r & WIZ Sn IR TIMEOUT ) // ARPto occured , SEND f a i l e d
{
f l a g = WIZ Sn IR SEND OK | WIZ Sn IR TIMEOUT ; // s e t SEND OK f l a g and c l e a r TIMEOUT f l a g
d m a w r i t e s o c k ( sock , WIZ Sn IR , &f l a g , 1 ) ;
}
} while ( ( i r & WIZ Sn IR SEND OK ) ! = WIZ Sn IR SEND OK ) ;
f l a g = WIZ Sn IR SEND OK ; // c l e a r SEND OK f l a g
d m a w r i t e s o c k ( sock , WIZ Sn IR , &f l a g , 1 ) ;
}
6
4
Schematics
7
Figure 1: Schematic of the Sensor Unit
C
B
1
vcc
gnd
vout
vcc
gnd
vout
vcc
gnd
vout
vcc
gnd
vout
vcc
gnd
vout
vcc
gnd
vout
A13xx
A13xx
A13xx
A13xx
A13xx
A13xx
S11
S10
S9
S8
S7
S6
S5
vcc
gnd
vout
A13xx
S4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
A11
A10
A09
A08
A07
A06
A05
A04
Vref
0.1uF
1uF
C11C31
Vcc
0.1uF
1uF
C10C30
Vcc
0.1uF
1uF
C9 C29
Vcc
0.1uF
1uF
C8 C28
Vcc
0.1uF
1uF
C7 C27
Vcc
0.1uF
1uF
C6 C26
Vcc
0.1uF
1uF
C5 C25
Vcc
0.1uF
1uF
2
R1
20k
1
2
200k
RV1
Ain
1
2
3
4
3
CONN_4
P1
1
2
3
4
5
6
7
8
9
10
11
12
NC
VinVin+
Vss
U1
MCP601
D1
Vcc
VI
5k
RV3
NCC
Vdd
Vout
NC
8
7
6
5
3
3
C36
vcc
i8
i9
i10
i11
i12
i13
i14
i15
e
s2
s3
Vdd
Vcc
0.1uF 1uF
C17
10uF
C19
Vcc
Power Supply
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
1
2
3
4
Vcc
0.1uF
1uF
A04
A05
A06
A07
A03
A02
A01
A00
C16
C37
Voltage reference
U2
VO
Multiplexer
1
10uF
C18
vout
i7
i6
i5
i4
CD74HC4067
i3
i2
U0
i1
i0
s0
s1
gnd
DIODE
Shifting Amplifier
1
2
3
4
Ain
A08
A09
A10
A11
A12
A13
A14
A15
Vdd
Vref
2
vcc
gnd
vout
3
GND
MCP1703
1uF
A13xx
2
C38
Vcc
P2
C4 C24
P0
CONN_4
A
1
CONN_3
8
0.1uF
A00
0.1uF
A01
0.1uF
0.1uF
0.1uF
0.1uF
A15
C15
C35
1uF
A14
C14
C34
1uF
A13
C13
C33
A12
0.1uF
C12
A03
0.1uF
C3
A02
1uF
1uF
C32
1uF
C23
1uF
C22 C2
1uF
C21 C1
1uF
C20 C0
4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
4
File: chimaera_sensor_unit.sch
Sheet: /
Title: Chimaera Sensor Unit (SU-16)
Size: A4
Date: 12 jun 2014
KiCad E.D.A.
Licensed under CERN OHL v.1.2
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
vcc
gnd
vout
vcc
gnd
vout
vcc
gnd
vout
vcc
gnd
vout
vcc
gnd
vout
vcc
gnd
vout
vcc
gnd
vout
vcc
gnd
vout
S15
A13xx
S14
A13xx
S13
A13xx
S12
A13xx
S3
A13xx
S2
A13xx
S1
A13xx
S0
A13xx
5
5
Rev: 8-3v3
Id: 1/1
C
B
A
Figure 2: Schematic of the DSP unit (STM32F303Cx part)
Y3
Y2
Y1
Y0
1
2
3
4
VI
U2
VO
MCP1703
GNDA
10uF
C10
FERR
FB1
2
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
1
2
3
4
5
6
7
8
9
10
GNDA
1
3
5
7
9
11
13
15
17
19
P2
2
4
6
8
10
12
14
16
18
20
1
2
3
4
1
2
3
4
+9V
4
2
X1
a0
a1
a2
gnd
a0
a1
a2
gnd
8MHz
U7
3
24AA025E48
U5
24LC64
vcc
wp
scl
sda
vcc
wp
scl
sda
OSC_OUT
OSC_IN
8
7
6
5
8
7
6
5
J1
0.1uF
C21
1
2
3
4
0.1uF
C23
SCL
SDA
SCL
SDA
R6
4.75k
R7
4.75k
SCL
4
5
6
SDA
+5VD
0.1uF
C2
U8
4
10nF
C6
D2-I
GND
D1-I
GNDA
4.7uF
C5
+3.3VADC
NUF2042
0.1uF
C4
D2-O
VBUS
D1-O
0.1uF
C3
+3.3V
3
2
1
1uF
C7
+3.3V
USBDM
USBDP
CP
MR
1
9
7
10
2
6
5
4
3
LED
1
MR
U6
R1
1k
5
74HC163
0.1uF
Pe
Cep
Cet
Cp
P3
P2
P1
P0
2
C22
LED
D3
Tc
Q0
Q1
Q2
Q3
15
14
13
12
11
Y0
Y1
Y2
Y3
SW1
9
8
7
12
11
+3.3V
+3.3V
PA2/USART2_TX/ADC1_IN3
PA1/ADC1_IN2
PA0/ADC1_IN1
VDDA
GNDA
nRST
PF1/OSC_OUT/I2C2_SCL
PF0/OSC_IN/I2C2_SDA
PC15/OSC32_OUT
nSS
SCK
MISO
MOSI
nINT
nRST
W5500.sch
W5500
RESET
BOOT0
PC14/OSC32_IN
PC13
VBAT
4
2
Licensed under CERN OHL v.1.2
ADC3
ADC1
ADC2
6
5
4
3
2
1
10
DPDT
OSC_IN
OSC_OUT
RESET
3
1
41
42
43
+3.3V
P3
from sensor units
+3.3V
+3.3VADC
DIODE
+9V
power in
P1
U4
STM32F303CX
P12
CONN_2
VDD
GND
PA13
PB12/SPI2_NSS/ADC4_IN3
PB13/SPI2_SCK/ADC3_IN5
PB14/SPI2_MISO/ADC4_IN4
PB15/SPI2_MOSI/ADC4_IN5
PA8
PA9/I2C2_SCL/USART1_TX
PA10/I2C2_SDA/USART1_RX
PA11/USB_DM/CAN_RX
PA12/USB_DP/CAN_TX
+3.3V
25
26
27
28
29
30
31
32
33
34
35
36
7
Rev: 4-3v3
Id: 1/2
RESET
USBDP
USBDM
SDA
SCL
BOOT0
1
2
3
4
5
SCL
6
SDA
7
C
B
A
6
File: chimaera_dsp_unit.sch
Sheet: /
Title: Chimaera DSP Unit
Size: A3
Date: 5 may 2014
KiCad E.D.A.
E
33uF
C16
10uF
39
E
1
2
+3.3V
+3.3V
D
1
2
F1
D1
FUSE 1
DIODE
D2
+
U1
2
1
C8
C1
C9
6
P11
CONN_6
D
C
B
+9V
+
3
1
GND
GND
P5
to sensor units
18pF
18pF
VO
from sensor units
R4
1k
1k
R2
LM1117
1.5k
R8
VI
+3.3V
R5
10k
R3
10k
5
44
4
46
PB9/I2C1_SDA/CAN_TX
+5VD
USB
+3.3V
+3.3V
CP
MR
BOOT0
45
PB8/I2C1_SCL/CAN_RX
3
+3.3V
37
PA14/I2C1_SDA/USART2_TX
2
+3.3V+3.3V+3.3V
40
PB4/SPI3_MISO/SPI1_MISO/USART2_RX
A
1
+3.3V
13
GNDA
+3.3VADC
48
VDD
PA3/USART2_RX/ADC1_IN4
47
GND
PA4/SPI1_NSS/SPI3_NSS/ADC2_IN1
14
BOOT0
PA7/SPI1_MOSI/ADC2_IN4
17
PA5/SPI1_SCK/ADC2_IN2
15
PB7/I2C1_SDA/USART1_RX
PB0/ADC3_IN12
18
PA6/SPI1_MISO/ADC2_IN3
16
PB6/I2C1_SCL/USART1_TX
PB1/ADC3_IN1
19
38
PA15/I2C1_SCL/USART2_RX/SPI3_NSS/SPI1_NSS
GND
PB5/SPI3_MOSI/SPI1_MOSI
PB2/ADC12_IN12
20
ADC4
ADC5
ADC6
ADC7
ADC8
ADC10
ADC9
LED
PB3/SPI3_SCK/SPI1_SCK/USART2_TX
PB11/USART3_RX
22
VDD
24
PB10/USART3_TX
21
2
23
1
9
Figure 3: Schematic of the DSP unit (WIZnet W5500 part)
C
B
1
C51
C52
18pF
18pF
X51
RCT
RXN
RXP
TCT
TXN
XO
1M
R51
R67
10
R66
49.9/1%
R65
49.9/1%
R69
82/1%
R68
82/1%
W3V3A
C53
+
2
0.1uF
C54
0.1uF
C55
0.1uF
C56
+3.3V
0.1uF
C58
LINKLED
ACTLED
RXN
RXP
0.1uF
C57
B51
2
R71
330
R70
330
RCT
TXP
TCT
TXN
YK
LEDY_K
YA
LEDY_A
GK
LEDG_K
GA
LEDG_A
8
6
RD-
5
RCT
4
RD+
3
TD-
2
TCT
1
TD+
120R@100MHz+3.3V
1
0.1uF
C59
10uF
+
C61
3
YELLOW
GREEN
RCV
XMIT
J6
J7
J8
J3
J2
J4
J5
J1
RJ45-TRANSFO
0.1uF
C60
3
J51
W3V3A
R52
12.4k
W3V3A
W3V3A
RXN
RXP
TXN
TXP
13
SHIELD
1
2
3
4
5
6
7
8
9
10
11
12
+3.3V
4
U51
W5500
C63
10nF
C62
4.7uF
4
File: W5500.sch
Sheet: /W5500/
Title: WIZnet W5500 MagJack
Size: A4
Date: 5 may 2014
KiCad E.D.A.
Licensed under CERN OHL v.1.2
TXN
TXP
GNDA
VCC3V3A
RXN
RXP
DNC
VCC3V3A
GNDA
EXRES1
VCC3V3A
NC
W3V3A
10uF
2
W3V3A
3
1
TXP
C64
W3V3A
4
2
10nF
XI
22nF
C66
10k
R54
10k
R53
10k
R56
10k
R55
10k
R58
10k
R57
10k
R60
10k
R59
+3.3V
R62
10k
INTn
MOSI
MISO
SCLK
SCSn
XO
XI/CLKIN
GND
VCC3V3
ACTLED
DUPLED
LINKLED
nRST
10k
R61
48
47
46
45
44
43
42
41
40
39
38
37
GNDA
NC
NC
PMODE0
PMODE1
PMODE2
RSVD
RSVD
RSVD
RSVD
RSVD
RTSn
NC
GNDA
VCC3V3A
GNDA
VCC3V3A
VBG
GNDA
TOCAP
VCC3V3A
1V2O
RSVD
SPDLED
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
XO
XI
MOSI
MISO
SCK
LINKLED
ACTLED
+3.3V
nINT
nSS
A
1
C65
W3V3A
6.8nF
6.8nF
C67
10
5
5
R64
10k
R63
10k
Rev: 1
Id: 2/2
+3.3V
25MHz
C
B
A

Download Report