royal13 (pdf, 14 MiB) - Infoscience

Nanosystems:
Technology,
Architectures and Applications
Giovanni De Micheli
Outline
  Introduction
  Technology
  Devices
  Circuits
  Architecture
  Communication infrastructure
  3D Integration
  Sensors
  Applications
  Conclusions
(c) Giovanni De Micheli
2
Nano-systems
Nano
  Nano-electronics:
 
 
 
 
CMOS < 32nm node
Silicon nanowires
Carbon nanotubes
Flatronics
  Nano-bio-sensing:
Systems
  Tera-scale systems:
  Heterogeneity
  Sensing, Processing,
Communication, SW
Transducers
  Complexity:
  Size compatibility
  Electro-chemistry
(c) Giovanni De Micheli
  Design
  Management
3
Outline
  Introduction
  Technology
  Devices
  Circuits
  Architecture
  Communication infrastructure
  3D Integration
  Sensors
  Applications
  Conclusions
(c) Giovanni De Micheli
4
The emerging nano-technologies
  System technology is build bottom-up,
starting from materials and their properties
  New devices exploit functional geometries at the
molecular level
  Quantum confinement
  There is a plethora of new materials and processing
steps/flows
  More than 50 elements in a regular CMOS process
  Enhanced silicon CMOS is likely to remain the main
manufacturing proces
(c) Giovanni De Micheli
5
Beyond CMOS
  Nano-technology provides us with new devices
[Close, Stanford]
[Infineon]
[Leblebici, EPFL]
  Can they mix and match with standard CMOS technology ?
  What is the added value?
(c) Giovanni De Micheli
6
22 nm Tri-Gate Transistors
[Courtesy: M. Bohr]
(c) Giovanni De Micheli
7
FinFETs versus SiNW FETs
(c) Giovanni De Micheli
8
Ambipolarity
  Device characteristics controlled by backgate voltage
  Four-terminal devices
  Back gate determines type: n or p
[Courtesy: Sacchetto, EPFL]
(c) Giovanni De Micheli
9
Double Independent gate SiNW FET
S
Source
Control gate
CG
Polarity
S
CG
PG
p-FET
D
Drain
D
S
CG
n-FET
D
gate
  Program the transistor to either p-type or n-type
10
Silicon Nanowire Transistors
  Gate all around transistors
  Double gate to control polarity
(c) Giovanni De Micheli
[Courtesy: De Marchi, EPFL] 11
Device Id/Vcg
Vds=2V
Vcg
Log( Id [A] )
Vpg
Vpg = 0V
Vpg = 2V
Vpg = 4V
0
2
Vcg [V]
3
4
[Courtesy: De Marchi, EPFL]
12
New Design Paradigm: Ambipolar Logic
  CMOS complementary logic efficient only for negative-unate
functions (INV, NAND, NOR…etc)
  Ambipolar logic is efficient for both unate and binate functions
  Optimal for XOR and XNOR dominated circuits
Negative Unate functions
INV
NAND2
Gnd
A
XOR2
B
Gnd
Gnd
Binate functions
Y
B
Vdd
Vdd
A
Vdd
Similar to regular CMOS
Only 4 transistors when compared to 8
transistors with a regular CMOS
(c) Giovanni De Micheli
[Courtesy: H. Ben Jamaa, ’08]" 13
Alternative logic families
Pseudo Logic
Static Logic
Transistor pair
A
B’
A’C
B
Y
A
B
C
VB
Single transistor
A
B’
A’
B’
Y
C
Y
A
B
C
VB
Y
A
B
C
A’
B’
A
B
C
(c) Giovanni De Micheli
14
Sea-of-Tiles (SoT)
  Homogeneous array of Tiles
Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile (c) Giovanni De Micheli
15
Sea-of-Tiles (SoT)
  Homogeneous array of Tiles
Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile (c) Giovanni De Micheli
16
Polarity
Drain
Control
Source
Dumbbell-stick diagrams
Transistor pairing Control gates connected together Dumbell-‐s,ck Transistor grouping Polarity gates connected together 176
Layout abstraction and regularity with Tiles
n1
G1
g1
Tile n6
G1
n2
G2
g2
n5
G2
n3
Two transistor pairs grouped together n4
XOR2 NAND2 (c) Giovanni De Micheli
[Courtesy: Bobba, DAC 12] 18
Outline
  Introduction
  Technology
  Devices
  Circuits
  Architecture
  Communication infrastructure
  3D Integration
  Sensors
  Applications
  Conclusions
(c) Giovanni De Micheli
19
System architectural trends
  Many-core processing
  Frequency scaling has leveled-off
  Exploit application-level parallelism
  On-chip communication
  Bottleneck for system performance
  Networks-on-Chip (NoC)
  Adopted as scalable interconnect
Intel Single-Chip Cloud Computer
[Courtesy: Howard, ISSCC 2010]
(c) Giovanni De Micheli
20
Networks-on-Chip Scalable Interconnect
  NoC modular architecture
  Network Interfaces (NIs)
  Switches
  Links
  Scalable
  Multiple parallel transactions
  Segmented point-to-point wires
  Used in prototypes and products
  Bone, Intel Polaris, SCC
  TI OMAP, Tilera TILE-Gx
xpipes library
[Courtesy: Stergiou DATE 2005]
(c) Giovanni De Micheli
21
Specialization for Power Efficiency
  Limited power budget for
mobile applications
  Trade-off programmability
for power-efficiency
  Specialized heterogeneous
IP-cores
  Communication is a
major power consumer
TI OMAP 5 application platform
(c) Giovanni De Micheli
  Traffic patterns are known
  Application specific NoC
design is needed
22
Application specific NoCs
?
  Challenges
  Many parameters (i.e., data-size, frequency, connectivity)
  Tools are required to find the best topology
  New technologies
  More IP-cores
  More constraints (i.e., 3D-IC vertical connectivity)
(c) Giovanni De Micheli
23
Design automation for NoCs
  Large design space
  What topology ?
  Which mapping ?
  Which routes to use ?
  Optimize parameters
  Link width, buffer sizes
  Simulate, verify, test
(c) Giovanni De Micheli
24
STHORM ANoC
64-bit G-ANoC-L2
DMA
CVP
CCPeripherals
DMA
CVP
Cluster
Processor
CCPeripherals
DMA
CVP
CC
CC
GALS
I/F
CCI
CC
CCI
Cluster
Processor
CCPeripherals
DMA
CVP
ENCore16
CCPeripherals
Cluster
Processor
ENCore16
Cluster
Processor
GALS
I/F
CCI
ENCore16
GALS
I/F
CCI
ENCore16
GALS
I/F
L2 tile (1MB)
CC
64-bit G-ANoC-L3
OCE
STxP70-V4B
DMA
SoC ports
32-KB TCDM
16-KB I$
ITC
FC PERIPHERAL
CVP
STM
Fabric Controller
[Courtesy: STMicroelectronics]
25
3D NoC Design
  Use NoCs to support Wide I/O
  Challenges:
  Meet application constraints in a 3D structure
-  Bandwidth, latency
-  Which topology, switches, layers and floorplan locations?
  Meet 3D technology constraints
-  Maximum available TSV constraints
-  Communication between adjacent layers
(c) Giovanni De Micheli
26
Extending 3D Integration to sensing
Custom micro-fabrication for
the bio‑layer
1000-10000 nm
Biosensor Array
90-600 nm
Analog Front-end
32-130nm
Digital Post-Processing
22-45nm
Memory
Technologies enabling low
noise operation for the
analog circuits
High speed/density CMOS
technologies
for
digital
circuits and memories
[ Courtesy Guiducci: 2010]
(c) Giovanni De Micheli
27
Disposable bio-layer
No need for cleaning. Bio-layer is disposed after
each measurement and CMOS layers are used
repeatedly
Increased sensitivity and array density due to
vertical interconnections from the bio-layer to the
readout electronics
Sophisticated algorithms for highly-specific target
identification run on-chip DSP and memory
[ C. Guiducci 2010]
(c) Giovanni De Micheli
28
Outline
  Introduction
  Technology
  Devices
  Circuits
  Architecture
  Communication infrastructure
  3D Integration
  Sensors
  Applications
  Conclusions
(c) Giovanni De Micheli
29
Memristive SiNW-based Biosensors
 
Crystalline, free-standing, Silicon Nanowires manifest memristive conductivity
due to the nano-scale of the fabricated structures
 
The voltage-gap between the forward and backward current minima in I/V
curves increases after NW functionalization with antibodies
29.31 nm
200 nm
F. Puppo, IEEE T. Nanobiosci., submitted
Increasing with
respect to humidity in
bio-modified NWs
Surface modification
with antibodies
In a controlled humidity range, Si NW device sense
antigen molecules (i.e., cancer biomarkers) thanks
to molecule up-take (immuno-recognition events)
displayed by voltage gap changes.
Small and constant in
bare NWs
S. Carrara et al. ,
Sens. Actuators B, 2012
30
CNT nanostructured sensors
metabolite
range
Cyclophosphamide detection - S.Carrara
Without
MWCNT !
(c) Giovanni De Micheli
31
CNT nano-structered electrodes
CARBON NANOTUBES
CNTs + PROBE ENZYMES
32
Outline
  Introduction
  Technology
  Devices
  Circuits
  Architecture
  Communication infrastructure
  3D Integration
  Sensors
  Applications
  Conclusions
(c) Giovanni De Micheli
33
Nanosystems applications
  Health:
  Personalized medicine, real-time medical monitoring
  Environment:
  Weather, pollution monitoring, rock stability
  Energy:
  Smart grid, data centers, energy-proportional computing
  Computing, communication, control
  Scientific and consumer applications
  Defense:
  Design of command and control systems
(c) Giovanni De Micheli
34
Nano-Tera.ch
  Health:
  Personalized medicine, real-time medical monitoring
  Environment:
  Weather, pollution monitoring, rock stability
  Energy:
  Smart grid, data centers, energy-proportional computing
(c) Giovanni De Micheli
35
Conclusions
  Nano-systems exploit the synergy of devices, circuits
and architectures
  New technologies enrich CMOS with novel devices
  Silicon nanowire and carbon nanotube devices
  Controlling ambipolarity can be efficiently used in logic design
  New architectures and design styles:
  Regularity of the fabric is key to robustness
  3-Dimensional integration gives an extra degree of freedom
  Hybridization of new technologies opens new frontiers
(c) Giovanni De Micheli
36
Thank You

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