D D ISCOBOLUS ESIGNS Rethinking Signal Integrity Using Embedded Passives Bill Gervasi [email protected] October 2014 Agenda History of memory signal termination Signal integrity on flyby buses Distributed termination for address buses Multi-drop socketed buses Flyby bus versus branched bus Line conditioning for multi-drop buses 2 Memory Bus Signal Termination History SDRAM DRAM DRAM DRAM DRAM CPU Data Bus DRAM DRAM DRAM DRAM CPU DDR1 VTT DRAM DRAM DRAM DRAM VTT VTT VTT VTT CPU DDR2-DDR4 VTT 3 Memory Bus Signal Termination History CPU DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM SDRAM-DDR1-DDR2 Address Bus DRAM DRAM DRAM DRAM DRAM DRAM DRAM VTT CPU VTT DRAM DDR3-DDR4 4 Signal Integrity on the Fly By 1 2 3 4 DRAM DRAM DRAM DRAM VTT CPU 1 2 3 4 5 Wishful Thinking 1 DRAM 2 DRAM 3 DRAM 4 DRAM fmax = 1136 MHz fmax = 1116 MHz fmax = 1089 MHz fmax = 1066 MHz Solution frequency = (f1 + f2 + f3 + f4) ÷ 4 = 1101 MHz, right? Of course not… Solution frequency = Min( f1 .. f4 ) = 1066 MHz So how do we maximize signal integrity at all DRAMs? 6 Distributed Address Termination DRAM DRAM DRAM DRAM DRAM DRAM DRAM VTT VTT VTT VTT VTT VTT VTT VTT CPU DRAM Problem is that termination resistors already take up 20% of available surface area Where would we put these hundreds of resistors? 7 Embedded Resistor Overview PCB Resist material fabbed into the PCB Cost is the same whether you have one resistor or 1000 8 Distributed Termination Using ER R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Resistance value is ratio of length to width times base resistance = ∗ R 9 Tuning Distributed Termination DRAM DRAM 1 VTT DRAM 2 VTT DRAM 3 VTT Typical termination is 36 W 4 VTT Simple distribution 4 x 36 = 144 W Tuned distribution (eg only) R1 = 135 W R2 = 140 W R3 = 149 W R4 = 154 W L 135 W 140 W 149 W 154 W Still 36 Wequivalent, however tuned for signal integrity at each point W Patent pending 10 3 DIMMs Per Channel CPU 11 DRAM DRAM DRAM VTT VTT VTT VTT CPU CPU Challenges in Supporting 3DPC DRAM VTT VTT VTT Empty sockets CPU Bus impedance different for each configuration Reflections off unloaded stubs DRAM DRAM VTT VTT 12 DRAM DRAM DRAM VTT VTT VTT VTT CPU CPU Desirable Configuration: Branched DRAM DRAM VTT VTT VTT DRAM CPU Reflections off unloaded stubs even worse than flyby Empty sockets VTT VTT 13 Line Conditioning Module Terminates every active signal on the bus Values match loading equivalent of 2 rank DIMM Signal RS CL RTT Data 15 W 3.7 pF 60 W Address 22 W 1.85 pF 100 W DDR3 DIMM example shown 14 Printed Embedded Capacitor Ceramic epoxy suspension Cu Cu Cu PCB 1 pF / 5 mm Cu Cu Cu 15 Termination Networks 60W 100W 3.7pF VSS 15W 1.85pF V T T VDD 60W 22W DQ DQ VTT A/C A/C CK CK# 16 Line Conditioning Module 2 layer PCB 300+ Printed resistors 150+ Printed capacitors Optional SPD: only mounted component can include thermal sensor 17 Using Line Conditioning LCM DRAM CPU VTT VTT LCM Line Conditioning Module VTT VTT LCM VTT Slot dependency eliminated CPU Bus impedance normalized DRAM VTT LCM VTT VTT 18 Nice Thermal Side Effect Low pressure zone Fully populated channel Empty socket Line Conditioning module installed 19 Concluding Memory bus termination still evolving Multi-drop socketed buses challenging Embedded resistors and capacitors provide unique solutions to these problems 20 Thank you! D D ISCOBOLUS ESIGNS
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