Method for Low Power Physical Design in EDI Savindar Fu/ Ken Du/ Alex Cai Jul.08.2014 TM External Use Making the World a Smarter Place. TM External Use 1 Freescale Kinetis Family Kinetis Microcontrollers (MCUs) consist of multiple hardware- and software-compatible ARM® Cortex®M0+ and -M4-based MCU series with exceptional low-power performance, scalability and feature integration. TM External Use 2 Agenda Kinetis Low Power Physical Implementation Floorplan Adjustment GigaOpt Application Leakage Power Optimization New Version EDI Application (13.12.000) Issues and Workarounds Fix Hold-Time Fix Transition-Time Critical Path Modules Placement TM External Use 3 Floorplan Adjustment Kinetis K Family Floorplan Challenge • Floorplan challenge due to huge memory size and many analog IPs • Timing closure challenge due to high performance requirement Kinetis L Family Floorplan Challenge • Die size reduction challenge Hard block placement is one key factor which will impact final chip utilization. It’s time worth to adjust hard placement to get a good SOG shape for easier routing and higher density. TM External Use 4 Floorplan Adjustment – K family Proj1 Initial Floorplan Adjustment Items: 1. Keep enough space for Flash output routing. 2. Keep enough space for Flash soft wrapper placement. TM External Use 5 Final Floorplan Floorplan Adjustment – L family Proj2 Adjustment Items: 1. Use partial padring to reduce die-size. 2. Highest density in floorplan stage. TM External Use 6 KL03 The world’s smallest and most energy efficient 32-bit MCU based on ARM® technology, smaller than a golf ball dimple. GigaOpt Application An ultra-fast and multi-threaded/highly scalable optimization technology that provides better quality of results (QoR) with faster runtime. Provides significant improvement in worst negative slack (WNS), total negative slack (TNS), and density while simultaneously reducing dynamic and leakage power across the board. TM External Use 7 GigaOpt Application – Proj1 Gate Count Utilization Total Power (mW) Proj1 (without GigaOpt) 709096 53.70% 133.6 -0.254 -1.943 Proj1 (with GigaOpt) 707105 53% 113.6 -0.185 -0.690 99.72% Timing TNS (ns) 98.70% 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 85.03% 72.83% 35.51% 0.5 Proj1 (without GigaOpt) Proj1 (with GigaOpt) Proj1 Compare (w/wo) Utilization Total Power(W) -0.5 -1 -2 TM External Use 8 Proj1 (without GigaOpt) 0 -1.5 Gate Count(M) Timing WNS (ns) Timing WNS (ns) Timing TNS (ns) Proj1 (with GigaOpt) Proj1 Compare (w/wo) GigaOpt Application – Proj2 Gate Count Utilization Total Power (mW) Proj2 (without GigaOpt) 3311051 46.80% 216.4 -0.437 -379.15 Proj2 (with GigaOpt) 3300296 46.10% 195.9 -0.349 -87.745 3.5 50 3 Timing TNS (ns) 79.86% 23.14% 0 2.5 2 1.5 Timing WNS (ns) 99.68% 98.50% Proj2 (with GigaOpt) -150 Proj2 (with GigaOpt) -200 -250 0.5 -300 0 Utilization Timing TNS (ns) Proj2 (without GigaOpt) Proj2 Compare (w/wo) Gate Count(M) Timing WNS (ns) -100 90.53% 1 -50 Proj2 (without GigaOpt) -350 Total Power(W) -400 TM External Use 9 Proj2 Compare (w/wo) Leakage Power Optimization For 90nm and below technologies, leakage is the main factor which dominates over the dynamic power. Current low power techniques in Kinetis Synthesis based Clock Gating Back Biasing Architecural Clock Gating Multiple Power Domains in SoG Power ShutOff (PSO) State Retention Power Gating (SRPG) Multi Threshold std Cells (HVT/SVT) Multi-bit Flops & Multi-bit SRPGs (Dual and Quad) Extended Gate Poly KL03 QFN packages VLLS0 mode leakage current TM External Use 10 Leakage Power Optimization in EDI – Proj1 Use optLeakagePower in EDI to optimize total leakage power of the design by swapping gates for gates with lower leakage power without degrading timing. SetOptMode leakagePowerEffort optLeakagePower High-VT lolk cell (%) 58.13% 10.51% Leakage Power 29.64uW 36.64uW Leakage Power Saving 19.10% TM External Use 11 New Version EDI Application (13.12.000) In EDI 13 release, GigaOpt technology is the default engine for optimization, including setup/hold/power optimization. GigaOpt simplifies the timing closure flow Gate Count Utilization Total Power (mW) Proj1 (with edi11.13) 709096 53.70% 133.6 -0.254 -1.943 Proj1 (with edi13.12) 707888 53.30% 96.17 0.002 0.000 99.83% Timing WNS (ns) Timing TNS (ns) 99.26% 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 71.98% Proj1 (with edi11.13) Proj1 (with edi13.12) Compare(13.12/11.13) Gate Count (M) Utilization TM External Use 12 Total Power (W) Agenda Kinetis Low Power Physical Implementation Floorplan adjustment GigaOpt application Leakage power optimization New version EDI application (13.12.000) Issues and Workarounds Fix hold time Fix transition time Critical Path modules placement TM External Use 13 Fix Hold-Time Issue Description • EDI cannot smartly select delay cell firstly for big violations but inserts small buffer chain instead Workaround • First step only use delay cells to fix big hold violations, then use buffers to fix other violations. This will reduce total gate count and area significantly. Suggestion • Suggest tool can handle this automatically TM External Use 14 Fix Transition-Time Issue Description • For some hard block pins with strict transition time requirement in timing model, EDI inserts buffer in each optimization stage, result in a redundant long buffer chain before those pins. Workaround • After placement, insert a big buffer for those pins and set don’t touch for them. Check final database to find redundant long buffer chains and delete them to save gate count and area. Suggestion • Suggest tool smartly identify those pins TM External Use 15 Critical Path Modules Placement Issue Description • A part of Kinetis projects have high frequency requirement. For some critical path related modules, EDI cannot smartly place them in a proper location thus lead to extra effort for optimization and gate count increasing. Workaround • Provide some guidelines for tool during placement stage for better timing Suggestion • Suggest tool enhancement on smart placement TM External Use 16 TM www.Freescale.com © 2014 Freescale Semiconductor, Inc. | External Use
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