ADDI r3,#2 LD r3,(r1) IF RF LDLI r1,#0 RFPC EX WB a 2 ALU ＋ rega IFPC 0 regc regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory ST (r1),r3 ADDI r3,#2 IF RF LD r3,(r1) RFPC EX LDLI r1,#0 WB a 2 regc ALU ＋ rega IFPC regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory 0 ST (r1),r3 IF RF ADDI r3,#2 RFPC EX LD r3,(r1) WB a 2 regc ALU ＋ rega IFPC regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory U パイプラインストール LD r3,(r1) NOP IF RF LDLI r1,#0 NOP RFPC EX WB a 2 regc ALU ＋ rega IFPC regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory 0 NOP LD r3,(r1) IF RF NOP RFPC NOP EX WB a 2 regc ALU ＋ rega IFPC regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory レジスタファイルのフォワーディング IF RF RFPC EX WB a 2 regc ALU ＋ rega IFPC regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory ストールサイクルの減少 NOP LD r3,(r1) IF RF LDLI r1,#0 NOP RFPC EX WB a 2 regc ALU ＋ rega IFPC regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory 0 ALUからのフォワーディング IF RF RFPC EX WB a 2 regc ALU ＋ rega IFPC regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory ADDI r3,#2 LD r3,(r1) IF RF LDLI r1,#0 RFPC EX WB a 2 regc ALU ＋ rega IFPC regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory ST (r1),r3 ADDI r3,#2 IF RF RFPC LD r3,(r1) LDLI r1,#0 EX WB a 2 regc ALU ＋ rega IFPC regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory ST (r1),r3 IF RF ADDI r3,#2 RFPC EX WB a 2 regc ALU ＋ rega IFPC regb c b IFIR Instruction Memory Imm. wadr RFIR Data Memory LD r3,(r1)
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